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may. 2001 ver 1.1 8-bit single-chip monitor microcontrollers hms9xc7132 hms9xc7134 users manual
additional information of this manual may be served by hynix semiconductor offices in korea or distributors and representatives listed at address directory. hynix semiconductor reserves the right to make changes to any information here in at any time without notice. the information, diagrams and other data in this manual are correct and reliable; however, hynix semicon- ductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. versi o n 1 . 1 published by mcu application team bjinlim@hynix.com blackjoe@hynix.com 2001 hynix semiconductor all right reserved.
hms9xc7132 / hms9xc7134 may.2001 ver1.1 1. overview . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2. block diagram . . . . . . . . . . . . . . . . . . 2 3. pin assignment . . . . . . . . . . . . . . . . . 3 3.1 40pdip pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3.2 42sdip pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4. package dimensions . . . . . . . . . . . . 5 4.1 40 pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4.2 42 sdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5. pin function . . . . . . . . . . . . . . . . . . . . 6 5.1 40dip pin description . . . . . . . . . . . . . . . . . . . . . . .7 5.2 42sdip pin description . . . . . . . . . . . . . . . . . . . . . .8 6. port structures . . . . . . . . . . . . . . . 9 7. electrical characteristics . . . 11 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . .11 7.2 recommended operating conditions . . . . . . . . . .11 7.3 dc electrical characteristics . . . . . . . . . . . . . . . . .11 7.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . .13 8. memory organization . . . . . . . . . 16 8.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 8.2 program memory . . . . . . . . . . . . . . . . . . . . . . . . . .17 8.3 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 8.4 list of sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 8.5 addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . .22 9. interrupts . . . . . . . . . . . . . . . . . . . . 24 9.1 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . .24 9.2 interrupt enable structure . . . . . . . . . . . . . . . . . . .26 9.3 interrupt priority structure . . . . . . . . . . . . . . . . . . .27 9.4 how interrupt are handled . . . . . . . . . . . . . . . . . . .29 10. power-saving mode . . . . . . . . . . . 30 10.1 power control register . . . . . . . . . . . . . . . . . . . . .30 10.2 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 10.3 power-down mode . . . . . . . . . . . . . . . . . . . . . . . .31 11. i/o ports . . . . . . . . . . . . . . . . . . . . . . 32 11.1 pin function selection . . . . . . . . . . . . . . . . . . . . . .33 12. oscialltor . . . . . . . . . . . . . . . . . . . 36 13. reset . . . . . . . . . . . . . . . . . . . . . . . . . 37 13.1 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 13.2 watchdog timer overflow . . . . . . . . . . . . . . . . . . . 37 13.3 low vdd voltage reset . . . . . . . . . . . . . . . . . . . . 37 14. watchdog timer . . . . . . . . . . . . . . 38 15. timer . . . . . . . . . . . . . . . . . . . . . . . . . 39 15.1 timer0 and timer1 . . . . . . . . . . . . . . . . . . . . . . . 39 15.2 timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 16. ddc interface . . . . . . . . . . . . . . . . 42 16.1 the sfrs for ddc interface . . . . . . . . . . . . . . . . 43 16.2 ddc1 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16.3 ddc2b protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16.4 ddc2ab/ddc2b+ protocol . . . . . . . . . . . . . . . . . 47 16.5 the ram buffer and ddc application . . . . . . . . . 48 17. i2c interface . . . . . . . . . . . . . . . . . 51 17.1 the sfrs for i2c interface . . . . . . . . . . . . . . . . . 52 17.2 programmers guide for i2c and ddc2 . . . . . . . 54 18. pulse width modulation . . . . . . 57 18.1 static pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 18.2 dynamic pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 19. sync processor . . . . . . . . . . . . . . 60 19.1 sync input signals . . . . . . . . . . . . . . . . . . . . . . . . 60 19.2 horizontal polarity correction . . . . . . . . . . . . . . . . 60 19.3 vertical polarity correction . . . . . . . . . . . . . . . . . . 60 19.4 vertical sync separation . . . . . . . . . . . . . . . . . . . . 60 19.5 horizontal sync. detection . . . . . . . . . . . . . . . . . . 62 19.6 vertical sync. detection . . . . . . . . . . . . . . . . . . . . 62 19.7 horizontal sync. generator . . . . . . . . . . . . . . . . . . 65 19.8 vertical sync. generator . . . . . . . . . . . . . . . . . . . . 66 19.9 hsync / vsync output driver . . . . . . . . . . . . . . 66 19.10 clamp pulse generator . . . . . . . . . . . . . . . . . . . 67 19.11 pattern generator . . . . . . . . . . . . . . . . . . . . . . . . 67 19.12 suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . 67 20. ad-convertor (adc) . . . . . . . . . . . 71 21. operation mode . . . . . . . . . . . . . . 73 21.1 otp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 21.2 64mqfp pinning and package dimensions . . . . 78 21.3 64mqfp pin description . . . . . . . . . . . . . . . . . . . 79 21.4 development tools . . . . . . . . . . . . . . . . . . . . . . . 81 22. instruction set . . . . . . . . . . . . . . . 82
hms9xc7132 / hms9xc7134 may.2001 ver1.1
hms9xc7132 / hms9xc7134 may.2001 ver1.1 1 hms9xc7132 / hms9xc7134 cmos single-chip 8-bit microcontroller for monitor 1. overview 1.1 description the hms9xc7132/4 is a single-chip microcontroller of the 80c51 family, which is dedicated for monitor application. it is parti cularly suitable for multi-sync computer monitor controller. this contains ddc interfaces to the pc host, sync-detector and sync-proces sor for auto-sync application, adc, static pwm, dynamic pwm and i 2 c bus interface for control of the video and deflection functions of the monitor. 1.2 features ? 80c51 core ? 32k bytes of rom for hms91c7132/4 (32k bytes of otp rom for hms97c7132/4) ? 256 bytes of ram and 256 bytes of xram for ddc operation ? uses an external crystal of 12 mhz ? one ddc compliant interface : - fully supports ddc1 with dedicated hardware - ddc2b, ddc2ab and ddc2b+ compliant dedi- cated hardware based on an i 2 c bus interface - ram buffer with programmable size, 128 bytes or 256 bytes, which can be used for ddc opera- tion or shared as system ram ? on-chip sync processor - hsync frequency with 12-bit resolution - vsync frequency with 12-bit resolution - hsync and vsync polarity - hsync and vsync presence detection - composite sync separation - free running sync. generation - clamping pulse output - pattern generation - separate input for a sog signal - missing pulse insertion option - hsync/ vsync change interrupt ? one multi-master/slave i2c interface (up to 400k bit/s) for control of other system ics ? eight 8-bit static pwm outputs for digital con- trol applications ? two 8-bit dynamic pwm outputs for various waveform generation ? one 8-bit adc with 4 input channels ? led driver port ; two port lines with 15 ma drive capability ? one 8-bit port only for i/o function ? 24 derivative i/o ports configurable for alterna- tive functions ? watchdog timer (524ms max.) ? on-chip low vdd voltage detect and reset (reset period: 524ms) ? operating temperature : 0 to 70 ? special idle and power-down modes with low power consumption ? single power supply : 4.5v to 5.5v device name rom size ram size i/o otp package hms91c7132/4 32k bytes mask rom 512 bytes 30(42dip) 32(42sdip) hms97c7132/4 40dip(hms91c7132/4), 42sdip(hms91c7132/4k)
hms9xc7132 / hms9xc7134 2 may.2001 ver1.1 2. block diagram vdd2 vss2 reset sda2 scl2 ach[3:0] vdd1 vss1 int0 xtal1 xtal2 dpwm0 to dpwm1 pw m0 to pw m7 sda1 scl1 p0 p 1 p 2 p 3 patout clam p hsyncout vsyncout vsyncin hsyncin sogin three 16-bit t im ers ( t0, t1, t2 ) cpu program memory (64kb) d ata memory (64kb) 8-bit adc i2c-bus serial i/o watch dog tim er parallel i/o ports & external bus sync. d etection & sync. process ddc interface 8x8-bit static pwm 2x8-bit dynamic pwm low v oltage r eset 80c51 core
hms9xc7132 / hms9xc7134 may.2001 ver1.1 3 3. pin assignment 3.1 40pdip pinning vsync-in hsync-in pwm1* /p2.3 pwm2* /p2.4 pwm3* /p2.5 pwm4* /p2.6 pwm5* /p2.7 hsync-out /p3.2 vsync-out /p3.3 pwm6* /int1 /p3.4 clamp/pwm /p3.5 padout /p3.6 sog /p3.7 v dd2 v ss2 scl1** /p1.0 sda1** /p1.1 ach0 /p1.2 ach1 /p1.3 ach2 /p1.4 pwm0* /p2.2 dpwm0* /p2.1 dpwm0* /p2.0 reset v dd1 v ss1 xtal2 xtal1 sda2** /p1.7 scl2** /p1.6 p0.7** p0.6** p0.5** p0.4** int0/vpp p0.3** p0.2** p0.1** p0.0** ach3 /p1.5 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 hms9xc7132 * : open-drain option ** : open-drain type pin 40dip (top view) vsync-in hsync-in pwm1* /p2.3 pwm2* /p2.4 pwm3* /p2.5 pwm4* /p2.6 pwm5* /p2.7 hsync-out /p3.2 vsync-out /p3.3 pwm6* /int1 /p3.4/clamp pwm /p3.5 padout /p3.6 sog /p3.7 p3.0 p3.1 scl1** /p1.0 sda1** /p1.1 ach0 /p1.2 ach1 /p1.3 ach2 /p1.4 pwm0* /p2.2 dpwm0* /p2.1 dpwm0* /p2.0 reset v dd1 v ss1 xtal2 xtal1 sda2** /p1.7 scl2** /p1.6 p0.7** p0.6** p0.5** p0.4** int0/vpp p0.3** p0.2** p0.1** p0.0** ach3 /p1.5 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 hms9xc7134 * : open-drain option ** : open-drain type pin 40dip (top view)
hms9xc7132 / hms9xc7134 4 may.2001 ver1.1 3.2 42sdip pinning vsync-in hsync-in pwm1* /p2.3 pwm2* /p2.4 pwm3* /p2.5 pwm4* /p2.6 pwm5* /p2.7 hsync-out /p3.2 vsync-out /p3.3 pwm6* /int1 /p3.4 clamp/pwm /p3.5 padout /p3.6 sog /p3.7 v dd2 v ss2 scl1** /p1.0 sda1** /p1.1 ach0 /p1.2 ach1 /p1.3 ach2 /p1.4 ach3 /p1.5 pwm0* /p2.2 dpwm0* /p2.1 dpwm0* /p2.0 p3.1 p3.0 reset v dd1 v ss1 xtal2 xtal1 sda2** /p1.7 scl2** /p1.6 p0.7** p0.6** p0.5** p0.4** int0/vpp p0.3** p0.2** p0.1** p0.0** 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 hms9xc7132k * : open-drain option ** : open-drain type pin 42sdip (top view) nc vsync-in hsync-in pwm1* /p2.3 pwm2* /p2.4 pwm3* /p2.5 pwm4* /p2.6 pwm5* /p2.7 hsync-out /p3.2 vsync-out /p3.3 pwm6* /int1 /p3.4/clamp pwm /p3.5 padout /p3.6 sog /p3.7 p3.0 p3.1 scl1** /p1.0 sda1** /p1.1 ach0 /p1.2 ach1 /p1.3 ach2 /p1.4 nc pwm0* /p2.2 dpwm0* /p2.1 dpwm0* /p2.0 reset v dd1 v ss1 xtal2 xtal1 sda2** /p1.7 scl2** /p1.6 p0.7** p0.6** p0.5** p0.4** int0/vpp p0.3** p0.2** p0.1** p0.0** ach3 /p1.5 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 hms9xc7134k * : open-drain option ** : open-drain type pin 42sdip (top view)
hms9xc7132 / hms9xc7134 may.2001 ver1.1 5 4. package dimensions 4.1 40 pdip 4.2 42 sdip 2.075 2.045 max 0.200 0.022 0.015 0.065 0.045 note 1. dimensions do not include mold flash and dambar protrusion. allowable mold flash is 0.010 inch. 2. controlling dimension : inch. 0.550 0.530 1.470 1.450 note 1. dimensions do not include mold flash and dambar protrusion. allowable mold flash is 0.010 inch. 2. controlling dimension : inch. 0.550 0.530
hms9xc7132 / hms9xc7134 6 may.2001 ver1.1 5. pin function v dd1 : supply voltage (digital). v ss1 : circuit ground (digital). v dd2 : supply voltage (analog). v ss2 : circuit ground (analog). reset : reset the mcu. xtal1 : input to the inverting oscillator amplifier and input to the internal main clock operating circuit. xtal2 : output from the inverting oscillator amplifier. hsync in : horizontal sync input vsync in : vertical sync input int0/v pp : external interrupt input. programming supply volt- age(during otp programming) port: the hms9xc7132 has four 8-bit ports (port0, port1, port2, and port3). port0 - port3 are the same as in the 80c51, with the exception of the additional functions of port1, port2 and port3. each has latch, sfr p0~p3 output driver and input buffer. p0.0~p0.7 : p0 is an 8-bit cmos bidirectional i/o port. p0 pins have not pull-up resister and open-drain port. it has the capability of drive led. however, while the alternative function is per- formed, the port type will remain the same. in case of application to extention of external memory, p0 outputted write/read byte and lower byte of external memory address. therefore when it is used as normal i/o port, p0 is open-drain driver and when it used as bus port, p0 is 3-state driver. p1.0~p1.7 : p1 is an 8-bit cmos bidirectional i/o port. because p1 pins have pull-up resister, it is called as quasi-bidirectional port. p2.0~p2.7 : p2 is an 8-bit cmos bidirectional i/o port. because p2 pins have pull-up resister, it is called as quasi-bidirectional port. . p3.0~p3.7 : p3 is an 8-bit cmos bidirectional i/o port. because p3 pins have pull-up resister, it is called as quasi-bidirectional port. port pin alternate function p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 no (only for i/o function) no (only for i/o function) no (only for i/o function) no (only for i/o function) no (only for i/o function) no (only for i/o function) no (only for i/o function) no (only for i/o function) port pin alternate function p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 scl1 (ddc-scl) sda1 (ddc-sda) ach0 ach1 ach2 ach3 scl2 (i 2 c-scl) sda2 (i 2 c-sda) port pin alternate function p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 dpwm0* dpwm1* pwm0* pwm1* pwm2* pwm3* pwm4* pwm5* port pin alternate function p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 reserved reserved hsync out vsync out pwm6* clamp/pwm7 patout sog
hms9xc7132 / hms9xc7134 may.2001 ver1.1 7 5.1 40dip pin description pin name (alternate) pin no. in/out (alter- nate) function basic alternate pwm0 /p2.2 1 i/o general i/o port p2.2 8-bit pulse width modulation output0 dpwm0 /p2.1 2 i/o general i/o port p2.1 8-bit dynamic pulse width modulation output0 dpwm0 /p2.0 3 i/o general i/o port p2.0 8-bit dynamic pulse width modulation output1 reset 4 i reset input v dd1 5 - power supply1(+5v) v ss1 6 - ground1 xtal2 7 o oscillator output pin for system clock xtal1 8 i oscillator input pin for system clock sda2 /p1.7 9 i/o general i/o port p1.7 i 2 c serial data i/o port scl2 /p1.6 10 i/o general i/o port p1.6 i 2 c serial clock i/o port p0.7 11 i/o general i/o port p0.7; adapted for led driver p0.6 12 i/o general i/o port p1.6; adapted for led driver p0.5 13 i/o general i/o port p0.5 p0.4 14 i/o general i/o port p0.4 int0 /v pp 15 i external interrupt input0; programming supply voltage (during otp programming) p0.3 16 i/o general i/o port p0.3 p0.2 17 i/o general i/o port p0.2 p0.1 18 i/o general i/o port p0.1 p0.0 19 i/o general i/o port p0.0 ach3 /p1.5 20 i/o general i/o port p1.5 adc channel3 input ach2 /p1.4 21 i/o general i/o port p1.4 adc channel2 input ach0 /p1.3 22 i/o general i/o port p1.3 adc channel1 input ach0 /p1.2 23 i/o general i/o port p1.2 adc channel0 input sda1 /p1.1 24 i/o general i/o port p1.1 i 2 c serial data i/o port for ddc interface scl1 /p1.0 25 i/o general i/o port p1.0 i 2 c serial clock i/o port for ddc interface v ss2 26 - ground2 v dd2 27 - power supply2(+5v) sogin /p3.7 28 i/o general i/o port p3.7 sync on green input patout /p3.7 29 i/o general i/o port p3.6 pattern out clamp /pwm7 / p3.5 /prog 30 i/o general output only port p3.5 program pulse input(during otp programming) clamp out ; 8-bit pulse width modulation output7 pwm6 /p3.4 / int1 31 i/o general i/o port p3.4 8-bit pulse width modulation output6; external interrupt input1 vsyncout /p3.3 32 i/o general i/o port p3.3 vertical sync output hsyncout /p3.2 33 i/o general i/o port p3.2 horizontal sync output pwm5 /p2.7 34 i/o general i/o port p2.7 8-bit pulse width modulation output5 pwm4 /p2.6 35 i/o general i/o port p2.6 8-bit pulse width modulation output4 pwm3 /p2.5 36 i/o general i/o port p2.5 8-bit pulse width modulation output3 pwm2 /p2.4 37 i/o general i/o port p2.4 8-bit pulse width modulation output2 table 5-1 port function description(40dip)
hms9xc7132 / hms9xc7134 8 may.2001 ver1.1 5.2 42sdip pin description the 42sdip type pin description is the same as the 40dip type pin description except for adding two pins(p3.1, p3.0) to it between pin no.4 and 5. pwm1 /p2.3 38 i/o general i/o port p2.3 8-bit pulse width modulation output1 hsyncin 39 i horizontal sync input vsyncin 40 i vertical sync input pin name (alternate) pin no. in/out (alter- nate) function basic alternate table 5-1 port function description(40dip)
hms9xc7132 / hms9xc7134 may.2001 ver1.1 9 6. port structures p0.0 - p0.5 p0.6 - p0.7 p1.0, p1.1, p1.6, p1.7, p2.0~7, p3.0, p3.1, p3.4, p3.6 p1.2 - p1.5 p3.2, p3.3, p3.5 p3.7 data cmos 5ma data cmos 10ma oen data cmos adc_enb oen data adc_in cmos internal reset data ttl oen data ttl
hms9xc7132 / hms9xc7134 10 may.2001 ver1.1 hsyncin, vsyncin int0/vpp reset xtal1, xtal2 ttl h ttl vpp detector vpp cmos pdb
hms9xc7132 / hms9xc7134 may.2001 ver1.1 11 7. electrical characteristics 7.1 absolute maximum ratings supply voltage......................................................-0.5 to +6.5 v storage temperature .......................................... -65 to +150 c voltage on any pin with respect to ground (v ss ) ..........................................................................-0.5 to v dd +0.5 note: stresses above those listed under "absolute maxi- mum ratings" may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliab ility. 7.2 recommended operating conditions 7.3 dc electrical characteristics (t a = 0~70 c, v dd =4.5~5.5v, v ss =0v ) , parameter symbol condition specifications unit min. max. supply voltage v dd f xin =12mhz 4.5 5.5 v operating frequency f xin v dd =4.5~5.5v 10 16 mhz operating temperature t opr -070 c symbol parameter condition specifications unit min. typ. max. supply vdd power supply voltage - 4.5 5.0 5.5 v idd power supply current fosc - 12mhz - tbd - ma vlvr low voltage reset - 3.3 3.7 4.1 v otp supply vdd power supply voltage - 4.5 5.0 5.5 v vpp programming voltage - - 12.75 - v iddp power supply current fosc - 4mhz - tbd - ma ipp programming current fosc - 4mhz - tbd - ma reset irst reset input pull-up resistance vin - 0v - 33 - m a iih input leakage current vin - vdd - 01 m a vil1 low-level input voltage - vss-0.5 - 0.3vdd v vih1 high-level input voltage - 0.7vdd - vdd+0.5 v xtal vop open bias voltage - - 2.5 - v ifr feedback resistor current vin - 5v - 10 - m a vil1 low-level input voltage - vss-0.5 - 0.3vdd v vih1 high-level input voltage - 0.7vdd - vdd+0.5 v int0, hsyncin, vsyncin iil input leakage current vin - vss -1 0 - m a iih input leakage current vin - vdd - 0 1 m a vil low-level input voltage - vss-0.5 - 0.3vdd v
hms9xc7132 / hms9xc7134 12 may.2001 ver1.1 vih high-level input voltage - 2.0 - vdd+0.5 v sog/p3.7 iil1 input leakage current vin - 0.45v -55 - -10 m a itl input transition current vin - 2.0v -650 - -65 m a iih input leakage current vin - vdd - 0 1 m a vil low-level input voltage - vss-0.5 - 0.8 v vih high-level input voltage - 2.0 - vdd+0.5 v vol low-level output voltage iol - 5ma 0 - 0.4 v voh high-level input voltage ioh - 5ma 3.5 - vdd v p0.0 to p0.5 iil input leakage current vin - vss -1 0 - m a iih input leakage current vin - vdd - 0 1 m a vil1 low-level input voltage - vss-0.5 - 0.3vdd v vih1 high-level input voltage - 0.7vdd - vdd+0.5 v vol low-level output voltage iol - 5ma 0 - 0.4 v p0.6 to p0.7 iil input leakage current vin - vss -1 0 - m a iih input leakage current vin - vdd - 0 1 m a vil1 low-level input voltage - vss-0.5 - 0.3vdd v vih1 high-level input voltage - 0.7vdd - vdd+0.5 v vol1 low-level output voltage iol - 10ma 0 - 0.4 v p2.0 to p2.7(bp2.0 to bp2.7) iil1 input leakage current vin - 0.45v -55 - -10 m a itl1 input transition current vin - 3.5v -650 - -65 m a iih input leakage current vin - vdd - 0 1 m a vil1 low-level input voltage - vss-0.5 - 0.3vdd v vih1 high-level input voltage - 0.7vdd - vdd+0.5 v vol low-level output voltage iol - 5ma 0 - 0.4 v voh high-level input voltage ioh - 5ma 3.5 - vdd v p1.0 to p1.7,p3.0,p3.1,p3.4,p3.6,p3.7 iil1 input leakage current vin - 0.45v -55 - -10 m a itl1 input transition current vin - 3.5v -650 - -65 m a iih input leakage current vin - vdd - 0 1 m a vil1 low-level input voltage - vss-0.5 - 0.3vdd v vih1 high-level input voltage - 0.7vdd - vdd+0.5 v vol low-level output voltage iol - 5ma 0 - 0.4 v voh high-level input voltage ioh - 5ma 3.5 - vdd v p3.2 to p3.3,p3.5 iil2 input leakage current vin - 0.45v -960 -320 m a itl2 input transition current vin - 2.0v -1240 -350 m a iih input leakage current vin - vdd 0 1 m a vil low-level input voltage - vss-0.5 0.8 v vih high-level input voltage - 2.0 vdd+0.5 v symbol parameter condition specifications unit min. typ. max.
hms9xc7132 / hms9xc7134 may.2001 ver1.1 13 7.4 ac characteristics (t a =-0~70 c, v dd =5.0v, v ss =0v) vol low-level output voltage iol - 5ma 0 0.4 v voh high-level input voltage ioh - 5ma 3.5 vdd v symbol parameter condition specifications unit min. typ. max. symbol parameter condition specifications unit min. typ. max. xtal fosc oscillator frequency vdd - 5v 10 12 16 mhz c1 xtal1 external cap. - - 20 - pf c2 xtal2 external cap. - - 20 - pf a/d converter v ain analog input voltage - vss - vdd v n aoff zero offset error - - - tbd lsb n fs full scale error - - 20 tbd lsb n acc overall accuracy - - - tbd lsb t conv conversion time fosc - 12mhz - 13 - m s ddc1 mode t h(vclk) vclk high time - 20 - - m sv t l(vclk) vclk low time - 20 - - m s t dov vclk to output valid fosc - 12mhz - - 680 m s t su(ddc1) ddc1 mode setup time - - tbd - m s t nc(in) cancelled noise input fosc - 12mhz - - 300 m s ddc2 mode f scl scl clock frequency - 0 - 100 khz t hd(sda) start condition hold time - 4.0 - - m s t su(sto) stop condition setup time - 4.0 - - m s t hd(dat) data hold time - 300 - - m s t su(sta) rstart(1) condition setup time - 4.7 - - m s t h(scl) scl high period - 4.0 - - m s t l(scl) scl low period - 4.7 - - m s hsyncin f (hsync) hsync input frequency - 12 - 120 khz t w(hsync) hsync input pulse width - 0.25 - 8 m s d (hsync) hsync duty cycle - - - 25 % vsyncin f (vsync) vsync input frequency - 32 - 200 hz t w(vsync) vsync input pulse width - 1 - 24 t p(h) d (vsync) vsync duty cycle - - - 25 % sogin
hms9xc7132 / hms9xc7134 14 may.2001 ver1.1 t p(eq) equalizing pulse period - - 0.5 - t p(h) t w(eq) equalizing pulse width - - 0.5 - t w(h) n (eq) equalizing pulse interval - - - 30 t p(h) hsyncout, vsyncout t d(hsync) hsync input to output - - - 100 ns t d,max(hsync) hsync input to output after missing hsyncin - - - 250 ns t d(hsync) vsync input to output - - - 180 ns t d,max(vsync) vsync input to output after missing vsyncin ---1 t p(h) t d(clamp) hsyncin to clamp - - - 100 ns symbol parameter condition specifications unit min. typ. max.
hms9xc7132 / hms9xc7134 may.2001 ver1.1 15 figure 7-1 timing on the i2c-bus figure 7-2 sync timing sda scl t hd(sda) t hd(dat) t su(dat) t su(sta) t su(sto) hsyncin hsyncout t d(hsync) t d,max(hsync) t w(hsync) clamp (front porch) t d(clamp) t d(clamp) clamp (back porch) vsyncin vsyncout t d(vsync) t d,max(vsync) t w(vsync)
hms9xc7132 / hms9xc7134 16 may.2001 ver1.1 8. memory organization the hms91c7132 has separate address spaces for program memory, data memory. program memory can only be read, not written to. it can be up to 32k bytes of program memory.(opt type: hms97c7132 32k bytes) data memory can be read and written to up to 256 bytes including the stack area.(internal ram) and 256bytes (external ram: 256bytes of xram0). figure 8-1 memory map and address spaces 8.1 registers this device has several registers that are the program counter (pc), accumulator (a), b register(b), the stack pointer (sp), the program status word(psw), general purpose regis- ter(r0~r7)and dptr(data pointer register). figure 8-2 configuration of registers accumulator: the accumulator is the 8-bit general purpose reg- ister, used for data operation such as transfer, temporary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with b register as shown below. figure 8-3 configuration of ba 16-bit registers b register: the b register is the 8-bit purpose register, used for an arithmatic operation such as multiply, division with accumu- lator stack pointer : the stack pointer is an 8-bit register used for oc- currence interrupts and calling out subroutines. stack pointer identifies the location in the stack to be access (save or re- store).the stack can be located at any position within 0000 h to 007f h of the internal data memory. the sp is not initialized by hardware, requiring to write the initial value (the location with 32k rom indirect only (mov @ri) direct(mov) or indirect (mov @ri) 0 127 255 direct (mov) or indirect (mov @ri ) indirect (movx @ri or movx @dptr) (xrams = 0) data memory program memory sfr xram ram a accumulator stack pointer program counter program status word sp pcl pch psw r0~r7 general purpose b b register register (bank0~3) dptr(dpl) dptr(dph) data pointer register two 8-bit registers can be used as a "ba" 16-bit register b a b a
hms9xc7132 / hms9xc7134 may.2001 ver1.1 17 which the use of the stack starts) by using the initialization rou- tine. normally, the initial value of 07 h is used and the stack area is 00 h to 7f h . program counter : the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indi- cates the address of the next instruction to be executed. in reset state, the program counter has reset routine address (pc h :0ff h , pc l :0fe h ). program status word : the program status word (psw) con- tains several bits that reflect the current state of the cpu and se- lect internal ram(00h~1fh:bank0~bank3). the psw is described in figure 8-4. it contains the carry flag, the auxiliary carry flag, the half carry (for bcd operation), the general pur- pose flag, the register bank select flags, the overflow flag, the undefined flag and parity flag. [carry flag cy] this flag stores any carry or not borrow from the alu of cpu after an arithmetic operation and is also changed by the shift in- struction or rotate instruction. [auxiliary carry flag ac] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. [register bank select flags rs0, rs1] this flags select one of four bank(00~07h:bank0, 08~0fh:bank1, 10~17h:bank2, 17~1fh:bank3)in internal ram. [overflow flag ov] this flag is set to 1 when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction exceeds +127(7f h ) or - 128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [parity flag p] this flag reflect on number of accumulators 1. if number of ac- uumulators 1 is odd, p=0. otherwise p=1. sum of adding acu- umulators 1 to p is always even. r0~r7 : general purpose register. data pointer register :data pointer register is 16-bit wide which consists of two-8bit registers, dph and dpl. this register is used as a data pointer for the data transmission with external data memory. figure 8-4 psw(program status word)register 8.2 program memory the program memory consists of rom : 32k bytes (hms91c7132) and 32k bytes (hms97c7132) 8.3 data memory the internal data memory is divided into four physically separat- ed part : 256 bytes of ram, 256 bytes of xram0, and 128 bytes of special function registers (sfrs) areas. ram four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower ram area. only one of these banks may be enabled at a time. the next 16 bytes, locations 32 through 47, sp 00 h stack area (30 h ~ 7f h ) bit 15 bit 0 87 hardware fixed 00 h ~7f h sp (stack pointer) could be in 00 h ~7f h . carry flag msb lsb reset value: 00 h psw auxiliary carry flag register bank select flag parity flag not assigned bit overflow flag register bank select flag general purpose flag cy ac f0 rs1 rs0 0v p (to select bank0~3 with rs0) (to select bank0~3 with rs1)
hms9xc7132 / hms9xc7134 18 may.2001 ver1.1 contain 128 directly addressable bit locations.the stack depth is only limited by the available internal ram space of 256 bytes. xram0 the 256 bytes of xram0 used to support ddc interface is also available for system usage by indirect addressing through the ad- dress pointer ddcadr and data i/o buffer rambuf. the ad- dress pointer(ddcadr) is equipped with the postincrement capability to facilitate the transfer of data in bulk (for details refer to ddc interface part). however, it is also possible to address the dram through movx command as usually used in the internal ram extension of 80c51 derivatives. xram0 0 to 255 is direct- ly addressable as external data memory locations 0 to 255 via movx-dptr instruction or via movx-ri instruction when the excons lsb is zero. since external access function is not available, any access to xram0 0 to 255 will not affect the ports. 7 6 5 4 3 2 1 0 table 8-1 extended control register(excon) figure 8-5 ram address ------- xrams bank3 bank2 bank1 bank0 00h 07h 08h 0fh 10h 17h 1fh 18h 2fh 2eh 2dh 2ch 2bh 2ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h ffh 0 7 8 15 16 23 31 24 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 255 (msb) (lsb) 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20 5f 5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50 4f 4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40 7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70 6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60 ~ ~ byte address (hex) bit address (he x) byte address (decimal) ~ ~
hms9xc7132 / hms9xc7134 may.2001 ver1.1 19 sfr the sfrs can only be addressed directly in the address range from 128 to 255. table 8.2 gives an overview of the special func- tion registers space. sixteen address in the sfrs space are both- byte and bit-addressable. the bit-addressable sfrs are those whose address ends in 0h and 8h. the bit addresses in this area are 80h to ffh. table 8-2 sfr memory map note: * the register that can be bit-addressing. f8 - hvgen cpgen vfh vfl hfh hfl ff f0 *b mdcon mdst vph hph vhpl f7 e8 *excon - - - ef e0 *acc-- ---- e7 d8 *s1con s1sta s1dat s1adr0 s2con s2sta s2dat s2adr df d0 *psw s1sdr1 rambuf ddcdat ddcadr ddccon d7 c8 *t2con - rc2l rc2h - - cf c0 - - c7 b8 *ip - bf b0 *p3 dpwmcon dpwm0 dpwm1 - ipa - b7 a8 *ie - pwm4 pwm5 pwm6 pwm7 wdtkey af a0 *p2 pwmcon pwm0 pwm1 pwm2 pwm3 wdtrst iea a7 98 -- 9f 90 *p1 p1sfs p2sfs p3sfs adat acon 97 88 *tcon tmod tl0 tl1 th0 th1 8f 80 *p0 sp dpl dph pcon 87
hms9xc7132 / hms9xc7134 20 may.2001 ver1.1 8.4 list of sfrs register description address r/w initial value 76543210 p0 port0 register 80h r/w 11111111 sp stack point register 81h r/w 00000111 dpl data pointer(low byte) register 82h r/w 00000000 dph data pointer(high byte) register 83h r/w 00000000 pcon power control register 87h r/w xx000000 tcon timer/counter control register 88h r/w 00000000 tmod timer/counter mode control register 89h r/w 00000000 tl0 timer/counter0 low byte register 8ah r/w 00000000 tl1 timer/counter1 low byte register 8bh r/w 00000000 th0 timer/counter0 high byte register 8ch r/w 00000000 th1 timer/counter1 high byte register 8dh r/w 00000000 p1 port1 register 90h r/w 11111111 p1sfs port1 special function selection register 91h r/w 00000000 p2sfs port2 special function selection register 92h r/w 00000000 p3sfs port3 special function selection register 93h r/w 00000000 adat adc data register 96h r/w 00000000 acon adc control register 97h r/w xx0x0001 p2 port2 register 0a0h r/w 11111111 pwmcon pwm control register 0a1h r/w 00000000 pwm0 pwm0 output register 0a2h r/w 11111111 pwm1 pwm1 output register 0a3h r/w 11111111 pwm2 pwm2 output register 0a4h r/w 11111111 pwm3 pwm3 output register 0a5h r/w 11111111 pwm4 pwm4 output register 0aah r/w 11111111 pwm5 pwm5 output register 0abh r/w 11111111 pwm6 pwm6 output register 0ach r/w 11111111 pwm7 pwm7 output register 0adh r/w 11111111 wdtkey watchdog key register 0aeh r/w 00000000 wdtrst watchdog timer reset register 0a6h r/w 00000000 iea interrupt enable register 0a7h r/w 0 xxxxx00 ie interrupt enable register 0a8h r/w 00000000 p3 port3 register 0b0h r/w 11111111 dpwmcon dynamic pwm control register 0b1h r/w 0xxxxx00 dpwm0 dynamic pwm0 output register 0b2h r/w 11111111 dpwm1 dynamic pwm1 output register 0b3h r/w 11111111 ipa interrupt priority register 0b6h r/w 0xxxxx00 ip interrupt priority register 0b8h r/w x0000000 t2con timer2 control register 0c8h r/w 0xxxx0xx rc2l reload low register 0cah r/w 00000000 rc2h reload high register 0cbh r/w 00000000 psw program status word register 0d0h r/w 00000000 rambuf ram buffer i/o interface register 0d4h r/w xxxxxxxx
hms9xc7132 / hms9xc7134 may.2001 ver1.1 21 ddcdat data shift register for ddc1 0d5h r/w 00000000 ddcadr ddc address pointer register 0d6h r/w 00000000 ddccon ddc mode status and ddc1 control register 0d7h r/w x 0 0 x 0000 s1con serial control register for ddc2 0d8h r/w 00000000 s1sta serial status register for ddc2 0d9h r 0 x 0 0 xxxx s1dat data shift register for ddc2 0dah r/w 00000000 s1adr0 serial address0 register for ddc2 0dbh r/w 0000000x s1adr1 serial address1 register for ddc2 0d3h r/w 0000000x s2con serial control register 0dch r/w 00000000 s2sta serial status register 0ddh r 0x00xxxx s2adr serial address register for i2c 0dfh r/w 0000000x s2dat data shift register for i2c 0deh r/w 00000000 acc accumulator 0e0h r/w 00000000 excon extended control register 0e8h r/w xxxxxxx0 b b register 0f0h r/w 00000000 mdcon mode indication register 0f1h r/w 0 0 0 x x 0 0 0 mdst mode status register 0f2h r x0000000 vph vertical scan period high byte register 0f3h r/w 00000000 hph horizontal scan period high byte register 0f4h r/w 00000000 vhpl v/h scan period high byte register 0f5h r/w 00000000 hvgen h/v pulse control register 0f9h r/w x 0 0 0 x 0 0 0 cpgen clamping pulse and pattern control register 0fah r/w 00000x00 vfh vertical free-running output pulse period high byte register 0fbh r/w 00100000 vfl vertical free-running output pulse period low byte register 0fch r/w 00001010 hfh horizontal free-running output pulse period high byte register 0fdh r/w 01100000 hfl horizontal free-running output pulse period low byte register 0feh r/w 00x11111 register description address r/w initial value 76543210
hms9xc7132 / hms9xc7134 22 may.2001 ver1.1 8.5 addressing mode the addressing modes in hms9xc7132 instruction set are as follows ? direct addressing ? indirect addressing ? register addressing ? register-specific addressing ? immediate constants addressing ? indexed addressing note that refer to chapter 22. instruction set those addressing modes and related instructions. (1) direct addressing in a direct addressing the operand is specified by an 8-bit address field in the instruction. only internal data ram and sfrs(80~ffh ram) can be directly addressed. example: mov a, 3eh ; a ram[3e] (2) indirect addressing in indirect addressing the instruction specifies a register which contains the address of the operand. both internal and external ram can be indirectly addressed. the address register for 8-bit addresses can be r0 or r1 of the selected register bank, or the stack pointer. the address register for 16-bit addresses can only be the 16-bit data pointer register, dptr. example: mov @r1, 40h ;[r1] h] (3) register addressing the register banks, containing registers r0 through r7, can be accessed by certain instructions which carry a 3-bit register spec- ification within the opcode of the instruction. instructions that ac- cess the registers this way are code efficient, since this mode eliminates an address byte. when the instruction is executed, one of four banks is selected at execution time by the two bank select bits in the psw. example; mov psw, #0001000b ; select bank0 mov a, #30h mov r1, a (4) register-specific addressing some instructions are specific to a certain register. for example, some instructions always operate on the accumulator, or data pointer, etc., so no address byte is needed to point it. the opcode itself does that. ? a 04 prog. memory 3e h 55 40 h ~ ~ ~ ~ 55 r1 prog. memory
hms9xc7132 / hms9xc7134 may.2001 ver1.1 23 (5) immediate constants addressing the value of a constant can follow the opcode in program mem- ory. example; mov a, #100h. (6)indexed addressing only program memory can be accessed with indexed addressing, and it can only be read. this addressing mode is intended for reading look-up tables in program memory. a 16-bit base register (either dptr or pc) points to the base of the table, and the ac- cumulator is set up with the table entry number. the address of the table entry in program memory is formed by adding the ac- cumulator data to the base pointer. example; movc a, @a+dptr 1ead h ~ ~ ~ ~ acc dptr 3a 1e73 prog. memory
hms9xc7132 / hms9xc7134 24 may.2001 ver1.1 9. interrupts there are interrupt requests from 9 sources as follows. ? int0 external interrupt ? int1 external interrupt ?timer0 interrupt ? timer1 interrupt ? timer2 interrupt ? ddc interrupt ? md interrupt ? vsync interrupt ? i2c interrupt 9.1 interrupt sources int0 external interrupt: ?the int0 can be either level-active or transition-active depend- ing on bit it0 in register tcon. the flag that actually generates this interrupt is bit ie0 in tcon. ? when an external interrupt is generated, the corresponding re- quest flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. ? i f the interrupt was level-activated then the interrupt request flag remains set until the requested interrupt is actually generated. then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. int1 external interrupt: ?t he int1 can be either level-active or transition-active depend- ing on bit it1 in register tcon. the flag that actually generates this interrupt is bit ie1 in tcon. ? when an external interrupt is generated, the corresponding re- quest flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. ? if the interrupt was level-activated then the interrupt request flag remains set until the requested interrupt is actually generated. then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. md interrupt: ?a md interrupt is generated by the hardware mode detector in case of mode change, horizontal or vertical. ? this flag has to be cleared by the software. vsync interrupt: ?the changing of the vsync level can generate an interrupt. this depends on the setting that is programmed in the mdcon- sfr. via this register it is possible to enable the edge of the vsync-signal that should generate the interrupt. both edges can be controlled separately. ? the interrupt flag has to be cleared by the software. ddc interrupt: ?the ddc interrupt is generated either by bit intr in the s1sta register for ddc2b/ddc2ab/ddc2b+ protocol or by bit ddc_int in the ddccon register for ddc1 protocol or by bit swhint bit in the ddccon register when ddc protocol is changed from ddc1 to ddc2. ? flags except the intr have to be cleared by the software. intr flag is cleared by hardware. i2c interrupt: ?the interrupt of the second i2c is generated by bit intr in the register s2sta. ? this flag is cleared by hardware.
hms9xc7132 / hms9xc7134 may.2001 ver1.1 25 timer0 and timer1 interrupt: ?timer0 and timer1 interrupts are generated by tf0 and tf1 which are set by an overflow of their respective timer/counter registers(except for timer0 in mode3). ?these flags are cleared by the internal hardware. timer2 interrupt: ?timer2 interrupt is generated by tf2 which is set by an overflow of timer2. ? this flag has to be cleared by the software. all of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. that is, interrupts can be generated or pending interrupts can be cancelled in software. figure 9-1 interrupt system int0 md timer0 i2c int1 ddc timer1 vsync not used timer2 high low interrupt polling sequence interrupt sources ie / iea ip / ipa priority global enable
hms9xc7132 / hms9xc7134 26 may.2001 ver1.1 9.2 interrupt enable structure each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable special function register ie and iea. all interrupt source can also be globally dis- abled by clearing bit ea in ie. table 9-1 interrupt enable register(ie: 0a8h) reset value:00000000b table 9-2 description of the ie bits table 9-3 interrupt enable register(iea: 0a7h) reset value:0xxxxx00b table 9-4 description of enable register(iea: 0a7h) 76543220 ea evsync et2 es et1 ex1 et0 ex0 bit symbol function 7ea disable all interrupts. 0 : no interrupt will be acknowledged 1 : each interrupt source is individually enabled or disabled by setting or clear ing its enable bit 6 evsync enable vsync interrupt 5et2 enable timer2 interrupt 4es not used 3et1 enable timer1 interrupt 2 ex1 enable external interrupt (int1) 1et0 enable timer0 interrupt 0 ex0 enable external interrupt (int0) 76543220 eddc-----ei2cemd bit symbol function 7eddc enable ddc interrupt 6 ex6 not used 5 ex5 not used 4 ex4 not used 3 ex3 not used 2 ex2 not used 1ei2c enable i2c interrupt 0emd enable md interrupt
hms9xc7132 / hms9xc7134 may.2001 ver1.1 27 9.3 interrupt priority structure each interrupt source can be assigned one of two priority levels. interrupt priority levels are defined by the interrupt priority spe- cial function register ip and ipa. 0 - low priority 1 - high priority a low priority interrupt may be interrupted by a high priority in- terrupt level interrupt. a high priority interrupt routine cannot be interrupted by any other interrupt source. if two interrupts of dif- ferent priority occur simultaneously, the high priority level re- quest is serviced. if requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. thus, within each priority level, there is a sec- ond priority structure determined by the polling sequence. this second priority structure is shown in table 9.5. table 9-5 priority levels note ? the priority within level structure is only used to resolve simultaneous requests of the same priority level. ? the md interrupt needs a higher priority then all the oth- er interrupts. this is to avoid that a mode change will not be serviced in time and that the setting of the s-curve is not up- dated in time. when the s-curve settings are not updated in time (after a mode change) the monitor may be damaged. table 9-6 interrupt priority register(ip: 0b8h) reset value: x0000000b table 9-7 description of the ip bits source priority within level int0 md timer0 i2c int1 ddc timer1 vsync timer2 1(highest) 9(lowest) 76543220 - pvsync pt2 ps pt1 px1 pt0 px0 bit symbol function 7- reserved 6 pvsync vsync interrupt priority level 5pt2 timer2 interrupt priority level 4ps not used 3pt1 timer1 interrupt priority level 2 px1 external interrupt (int1) priority level 1pt0 timer0 interrupt priority level 0 px0 external interrupt (int0) priority level
hms9xc7132 / hms9xc7134 28 may.2001 ver1.1 table 9-8 interrupt priority register(ipa: 0b6h) reset value: 0xxxxx00b table 9-9 description of the ipa bits 76543220 pddc-----pi2cpmd bit symbol function 7pddc ddc interrupt priority level 6 px6 not used 5 px5 not used 4 px4 not used 3 px3 not used 2 px2 not used 1pi2c i2c interrupt priority level 0pmd md interrupt priority level
hms9xc7132 / hms9xc7134 may.2001 ver1.1 29 9.4 how interrupt are handled the interrupt flags are sampled at s5p2 of every machine cycle. the samples are polled during following machine cycle. if one of the flags was in a set condition at s5p2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an lcall to the appropriate service routine, provided this h/w generated lcall is not blocked by any of the following condi- tions : ? an interrupt of equal priority or higher priority level is al- ready in progress. ? the current machine cycle is not the final cycle in the ex- ecution of the instruction in progress. ? the instruction in progress is reti or any access to the interrupt priority or interrupt enable registers. the polling cycle is repeated with each machine cycle, and the values polled are the values that were present at s5p2 of the pre- vious machine cycle. note that if an interrupt flag is active but be- ing responded to for one of the above mentioned conditions, if the flag is still inactive when the blocking condition is removed, the denied interrupt will not be serviced. in other words, the fact that the interrupt flag was once active but not serviced is not remem- bered. every polling cycle is new. the processor acknowledges an interrupt request by executing a hardware generated lcall to the appropriate service routine. the hardware generated lcall pushes the contents of the pro- gram counter on to the stack (but it does not save the psw) and reloads the pc with an address that depends on the source of the interrupt being vectored to as shown in table 9-10. execution proceeds from that location until the reti instruction is encountered. the reti instruction informs the processor that the interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the program counter. exe- cution of the interrupted program continues from where it left off. note that a simple ret instruction would also return execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future interrupts impossible. table 9-10 vector addresses source vector address int0 0003h md 004bh timer0 000bh i2c 0043h int1 0013h ddc 003bh timer1 001bh vsync 0033h timer2 002bh
hms9xc7132 / hms9xc7134 30 may.2001 ver1.1 10. power-saving mode two software selectable modes of reduced power consumption are implemented. ? idle mode ? power-down mode the following functions are switched off when the microcontroller enters the idle mode. ? cpu (halted) ? i2c interface (halted) ? pwm0 to pwm7 and dpwm0 to dpwm2 (reset, output = high) ? 8-bit adc (aborted if conversion in progress) the following functions remain active during idle mode. these functions may generate an interrupt or reset and thus terminate the idle mode. ? timer0, timer1 and timer2 ? watchdog timer ? ddc interface ? external interrupt ? mode detection in power-down mode, the system clock is halted. both the oscillator will be stopped after setting the bit pd in pcon. 10.1 power control register the modes idle and power-down are activated by software via the pcon register. table 10-1 power control register(pcon:87h) reset value:xx000000b table 10-2 description of the pcon bits 76543220 - - lvren lvrls gf1 gf0 pd idl bit symbol function 7 to 6 - not used 5 lvren enable low voltage reset 4lvrls select low vdd level ; 3.7v or 3.5v 3gf1 general purpose flag bit 2gf0 general purpose flag bit 1pd activate power-down mode 0idl activate idle mode
hms9xc7132 / hms9xc7134 may.2001 ver1.1 31 table 10-3 external pin status during idle and power-down modes 10.2 idle mode the instruction that sets pcon.0 is the last instruction executed in the normal operating mode before idle mode is activated. once in the idle mode, the cpu status is preserved in its entirety : stack pointer, program counter, program status word, accumulator, ram and all other registers maintain their data during idle mode. there are three ways to terminate the idle mode. ? activation of any enabled interrupt x0, t0, x1, t1 etc. will cause pcon.0 to be cleared by hardware terminating idle mode. the interrupt is serviced, and following return from interrupt instruction reti, the next instruction to be execut- ed will be the one which follows the instruction that wrote a logic 1 to pcon.0. ? external hardware reset : the hardware reset is required to be active for two machine cycle to complete the reset op- eration. ? internal watchdog reset : the microcontroller restarts after 3 machine cycles in all cases. 10.3 power-down mode the instruction that sets pcon.1 is the last executed prior to go- ing into the power-down mode. once in power-down mode, the oscillator is stopped. the contents of the on-chip ram and the special function register are preserved. the power-down mode can be terminated by an external reset in the same way as in the 80c51 (but sfrs are cleared due to re- set). mode memory port0-3 sync pwm i2c ddc - - idle intenal data on high high-z on - - power-down intenal data high high high-z high-z - -
hms9xc7132 / hms9xc7134 32 may.2001 ver1.1 11. i/o ports the hms9xc7132 has four 8-bit ports (port0, port1, port2 and port3). port0 - port3 are the same as in the 80c51, with the ex- ception of the additional functions of port1, port2 and port3. all ports are bidirectional and pins of which the alternative function is not used may be used as normal bidirectional i/os except port3.2, port3.3 and port3.5(these pins can be only used as the output). the use of port1- port3 pins as alternative functions are carried out automatically by the hms9xc7132 provided the associated sfr bit is set high.port0 is the type of open-drain i/o. port0.6 and port0.7 have the capability to drive led. fig. 11.1 shows the port structure. figure 11-1 standard output with the open-drain port the alternative function for port1, port2 and port3 can be described as follows. ? port 0 : no alternative function. ? port 1 : p1.0 is combined with the scl1 interface line(open-drain) p1.1 is combined with the sda1 interface line (open-drain) p1.2 is combined with the ach0 interface line (high-z) p1.3 is combined with the ach1 interface line (high-z) p1.4 is combined with the ach2 interface line (high-z) p1.5 is combined with the ach3 interface line (high-z) p1.6 is combined with the scl2 interface line (open-drain) p1.7 is combined with the sda2 interface line (open-drain) ? port 2 : p2.0 is combined with the dynamic pwm0 interface line(open-drain or push-pull) p2.1 is combined with the dynamic pwm1 interface line (open-drain or push-pull) p2.2 is combined with the static pwm0 interface line (open-drain or push-pull) p2.3 is combined with the static pwm1 interface line (open-drain or push-pull) p2.4 is combined with the static pwm2 interface line (open-drain or push-pull) p2.5 is combined with the static pwm3 interface line (open-drain or push-pull) p2.6 is combined with the static pwm4 interface line (open-drain or push-pull) p2.7 is combined with the static pwm5 interface line (open-drain or push-pull) ? port 3 : p3.0 has not alternative function. p3.1 has not alternative function. p3.2 is combined with the hsyncout interface line (push-pull) p3.3 is combined with the vsyncout interface line (push-pull) p3.4 is combined with the pwm6 interface line (open-drain or push-pull) p3.5 is combined with the clamp or pwm7 interface line (push-pull) p3.6 is combined with the patout interface line (push-pull) p3.7 is combined with the sog interface line (pull-up) i/o pin port data input data special data / gnd special function select 0 1 enable / data
hms9xc7132 / hms9xc7134 may.2001 ver1.1 33 11.1 pin function selection special function selection registers(pxsfs) several sfr(p1sfs/p2sfs/p3sfs)s are used to select the port-function or the alternative function of the external pin. ? p1sfs(port1 special function selection register) table 11-1 p1sfs bits(91h) table 11-2 description of the p1sfs bits 76543220 p1sfs7 p1sfs6 p1sfs5 p1sfs4 p1sfs3 p1sfs2 p1sfs1 p1sfs0 bit symbol function reset 7p1sfs7 the selection of the pin function. 0 : pin 9 has p1.7 function. 1 : pin 9 has sda2 function. 0 6p1sfs6 the selection of the pin function. 0 : pin 10 has p1.6 function. 1 : pin 10 has scl2 out function. 0 5p1sfs5 the selection of the pin function. 0 : pin 20 has p1.5 function. 1 : pin 20 has ach3 out function. 0 4p1sfs4 the selection of the pin function. 0 : pin 21 has p1.4 function. 1 : pin 21 has ach2 out function. 0 3p1sfs3 the selection of the pin function. 0 : pin 22 has p1.3 function. 1 : pin 22 has ach1 out function. 0 2p1sfs2 the selection of the pin function. 0 : pin 23 has p1.2 function. 1 : pin 23 has ach0 out function. 0 1p1sfs1 the selection of the pin function. 0 : pin 24 has p1.1 function. 1 : pin 24 has sda1 out function. 0 0p1sfs0 the selection of the pin function. 0 : pin 25 has p1.0 function. 1 : pin 25 has scl1 out function. 0
hms9xc7132 / hms9xc7134 34 may.2001 ver1.1 ? p2sfs(port2 special function selection register) table 11-4 description of the p2sfs bits 76543220 p2sfs7 p2sfs6 p2sfs5 p2sfs4 p2sfs3 p2sfs2 p2sfs1 p2sfs0 table 11-3 p2sfs bits(92h) bit symbol function reset 7p2sfs7 the selection of the pin function. 0 : pin 34 has p2.7 function. 1 : pin 34 has pwm5 function. 0 6p2sfs6 the selection of the pin function. 0 : pin 35 has p2.6 function. 1 : pin 35 has pwm4 out function. 0 5p2sfs5 the selection of the pin function. 0 : pin 36 has p2.5 function. 1 : pin 36 has pwm3 out function. 0 4p2sfs4 the selection of the pin function. 0 : pin 37 has p2.4 function. 1 : pin 37 has pwm2 out function. 0 3p2sfs3 the selection of the pin function. 0 : pin 38 has p2.3 function. 1 : pin 38 has pwm1 out function. 0 2p2sfs2 the selection of the pin function. 0 : pin 1 has p2.2 function. 1 : pin 1 has pwm0 out function. 0 1p2sfs1 the selection of the pin function. 0 : pin 2 has p2.1 function. 1 : pin 2 has dpwm1 out function. 0 0p2sfs0 the selection of the pin function. 0 : pin 3 has p2.0 function. 1 : pin 3 has dpwm0 out function. 0
hms9xc7132 / hms9xc7134 may.2001 ver1.1 35 ? p3sfs(port3 special function selection register) table 11-5 p3sfs bits(93h) table 11-6 description of the p3sfs bits 76543220 p3sfs7 p3sfs6 p3sfs5 p3sfs4 p3sfs3 p3sfs2 p3sfs1 p3sfs0 bit symbol function reset 7p3sfs7 the selection of the pin function. 0 : pin 28 has p3.7 function. 1 : pin 28 has sog input function. 0 6p3sfs6 the selection of the pin function. 0 : pin 29 has p3.6 function. 1 : pin 29 has patout out function. 0 5p3sfs5 the selection of the pin function. 0 : pin 30 has p3.5 function. 1 : pin 30 has clamp or pwm7 out function. 0 4p3sfs4 the selection of the pin function. 0 : pin 31 has p3.4 function. 1 : pin 31 has pwm6 out function. 0 3p3sfs3 the selection of the pin function. 0 : pin 32 has p3.3 function. 1 : pin 32 has vsyncout function. 0 2p3sfs2 the selection of the pin function. 0 : pin 33 has p3.2 function. 1 : pin 33 has vsyncout function. 0 1p3sfs1 the selection of the pin function. reserved 0 0p3sfs0 the selection of the pin function. reserved 0
hms9xc7132 / hms9xc7134 36 may.2001 ver1.1 12. oscialltor the oscillator circuit of the hms9xc7132 is a single stage invert- ing amplifier in a pierce oscillator configuration. the circuitry between xtal1 and xtal2 is basically an inverter biased to the transfer point. either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuit. both are operated in parallel resonance. xtal1 is the high gain amplifier input, and xtal2 is the out- put. to drive the hms9xc7132 externally, xtal1 is driven from an external source and xtal2 left open-circuit. figure 12-1 oscillator configuration main clock minimum instruction cycle time (ex:nop ; f ex 12clock is needed) 12mhz 1us xtal1 xtal2 xtal1 xtal2 external clock 10 ~ 16mhz reset vdd reset vdd 4.2v ideal standard; r=10k c=10uf (recommanded) reset ic r c
hms9xc7132 / hms9xc7134 may.2001 ver1.1 37 13. reset there are three ways to invoke a reset and initialize the hms9xc7132. via the external reset pin via the watchdog timer overflow via low vdd voltage reset each reset source will cause an internal reset signal active. the cpu responds by executing an internal reset and puts the internal registers in a defined state. figure 13-1 the reset mechanism 13.1 external reset the reset pin reset is connected to a schmitt trigger for noise reduction. a reset is accomplished by holding the reset pin low for at least 2 machine cycles (24 system clock), while the oscillator is running. an automatic reset can be obtained by switching on vdd, if the reset pin is connected to gnd via a capacitor and to the vdd via resistor. the capacitor should be at least 10uf. the increase of the reset pin voltage depends on the capacitor. the voltage must remain below the higher threshold for at mini- mum the oscillator start-up time plus 2 machine cycles. 13.2 watchdog timer overflow the length of the output pulse from the wdt is over 2048 machine cycles. in chapter 14, the watchdog timer is described in more detail. 13.3 low vdd voltage reset when vdd is below 3.7v, the built-in low voltage detector generates an internal reset signals. the reset signal will be low dur ing 2ms @12mhz after the voltage is higher than 3.7v. wdt lvr s q r 2.0ms timer reset rstout cpu& peri. nc
hms9xc7132 / hms9xc7134 38 may.2001 ver1.1 14. watchdog timer the hardware watchdog timer (wdt) resets the hms9xc7132 when it overflows. the wdt is intended as a recovery method in situations where the cpu may be subjected to a software upset. to prevent a system reset the timer must be reloaded in time by the application software. if the processor suffers a hardware/soft- ware malfunction, the software will fail to reload the timer. this failure will result in a reset upon overflow thus preventing the processor running out of control. in the idle mode the watchdog timer and reset circuitry remain ac- tive. the wdt consists of a 19-bit counter, the watchdog timer reset(wdtrst) sfr and watchdog key register(wdt- key).since the wdt is automatically enabled while the proces- sor is running. the user only needs to be concerned with servicing it.the 19-bit counter overflows when it reaches 524288(3fffh). the wdt increments once every machine cycle. this means the user must reset the wdt at least every 524288 machine cycles (524ms @12mhz). to reset the wdt the user- must write 01eh and then 0e1h to wdtrst. wdtrst is a write only register. the wdt count cannot be read or written. the watchdog timer is controlled by the watchdog key register, wdtkey. only pattern 01010101(=55h), disables the watch- dog timer. the rest of pattern combinations will keep the watch- dog timer enabled. this security key will prevent the watchdog timer from being terminated abnormally when the function of the watchdog timer is needed. in idle mode, the oscillator continues to run. to prevent the wdt from resetting the processor while in idle, the user should always set up a timer that will periodically exit idle, service the wdt, and re-enter idle mode. table 14-1 watchdog timer key register (wdtkey : 0aeh) reset value:00000000b table 14-2 description of the wdtkey bits table 14-3 watchdog timer clear register (wdtrst : 0a6h) reset value:00000000b table 14-4 description of the wdtrst bits example program; watch dog timer reset & wdt_refresh part reset: clr ea mov psw, #00 mov sp, #stack_data; mov wdtkey, #55h ; watchdog stop wdt_refresh: mov wdtrst, #1eh ; watchdog timer reset mov wdtrst, #0e1h ; watchdog timer reset mov wdtkey, #0f0h ; watchdog start ret 76543220 wdtkey7 wdtkey6 wdtkey5 wdtkey4 wdtkey3 wdtkey2 wdtkey1 wdtkey0 bit symbol function 7 to 0 wdtkey7 to wdtkey0 enable or disable watchdog timer. 01010101(=55h) : disable watchdog timer. others : enable watchdog timer. 76543220 wdtrst7 wdtrst6 wdtrst5 wdtrst4 wdtrst3 wdtrst2 wdtrst1 wdtrst0 bit symbol function 7 to 0 wdtkey7 to wdtkey0 enable or disable watchdog timer. 01010101(=55h) : disable watchdog timer. others : enable watchdog timer.
hms9xc7132 / hms9xc7134 may.2001 ver1.1 39 15. timer hms9xc7132 has two 16-bit timers/counters (timer0, timer1) to be placed in 80c51 core and one 16-bit auto-reload timer(timer2) for dynamic pwm. 15.1 timer0 and timer1 the external input pin that the timer/counter0 and timer/ counter1 in 80c51 core have is eliminated. in the timer function, timer register is incremented every machine cycle. thus, you can think of it as counting machinecycles. since a machine cycle con- sists of 12 oscillator periods, the count rate is 1/12 of the oscilla- tor frequency. timer 0, timer 1 have four operating modes. these modes is se- lected by bit-pairs(m1, m0) in tmod. table 15-1 timer mode control register(tmod) reset value:00000000b table 15-2 description of the tmod bits 76543220 gate c/t m1 m0 gate c/t m1 m0 bit symbol function 7,3 gate gating control when set. timer x is enabled only while intx pin is high and trx control bit is set. when cleared timerx is enabled whenever trxcontrol bit is set. 6,2 c/t timer or counter selector 0 : timer 1 : counter, not supported. 7 to 0 m1, m0 0, 0 0, 1 1, 0 1, 1 operating modes 8-bit timer thx with tlx as 5-bit prescaler 16-bit timer thx and tlx are cascaded : there is no prescaler 8-bit auto-reload timer thx holds a value which is to be reloaded into tlx each time it overflows. timer0 : tl0 is an 8-bit timer controlled by the standard timer 0 control bit. : th0 is an 8-bit timer only controlled by timer 1 control bit. timer1 : timer 1 stopped.
hms9xc7132 / hms9xc7134 40 may.2001 ver1.1 table 15-3 timer control register(tcon) reset value:00000000b table 15-4 description of the tcon bits 15.2 timer2 timer2 is a 16-bit auto-reload timer. the 16-bit capture mode, baud rate generation mode and an event counter function that the timer/counter2 in 80c52 core has are eliminated. since the clock of this timer comes from the system oscillator, timer2 can be used to count a time period more accurately comparing with timer0 and timer1, but the longest period is limited as 65536 x (tosc/2). the interval between interrupt = 65536 x (2 x tosc) - (rc2h x 256 + rc2l) x (2 x tosc) the maximum interrupt period = 65536 x (2 x tosc) table 15-5 timer2 control register (t2con : 0c8h) reset value:0xxxx0xxb table 15-6 description of the tcon bits 76543220 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit symbol function 7 tf1 timer1 overflow flag. set by hardware on timer oveflow. cleared by hardware when processor vectors to interrupt routine. 6 tr1 timer1 run control bit. set/cleared by software to turn timer on/off . 5 tf0 timer0 overflow flag. set by hardware on timer oveflow. cleared by hardware when processor vectors to interrupt routine. 4 tr0 timer0 run control bit. set/cleared by software to turn timer on/off . 3ie1 interrupt1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. 2it1 interrupt1 type control bit. set/cleared by software to specified falling edge/low level triggered external interrupts. 1ie0 i nterrupt0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. 0it0 interrupt0 type control bit. set/cleared by software to specified falling edge/low level triggered external interrupts. 76543220 tf2----tr2-- bit symbol function 7 tf2 timer2 overflow flag. set by hardware on timer overflow. must be cleared by software. 6 to 3 - reserved 2 tr2 timer2 run control bit. set/cleared by software to turn timer on/off. 1 to 0 tr0 reserved
hms9xc7132 / hms9xc7134 may.2001 ver1.1 41 table 15-7 reload/capture high register (rc2h : 0cbh) reset value:00000000b table 15-8 reload/capture low register (rc2l : ocah) reset value:00000000b example program; timer initial & timer1 interrupt part initial: ; mov ip, #00h; interrupt priority mov pcon, #00; mov tcon, #01010000b; t1, t0 enable mov tmod, #00010001b; 16 bit timer set mov ie, #11001000b; global en(7), vsync(6), timer1(3) t1_isr: push psw; psw push dph; dptr push dpl; push acc; a push 00h; r0 push 01h; r1 push 02h; r2 mov th1, #0f0h; f060h to generate 4msec mov tl1, #60h; 76543220 rc2h7 rc2h6 rc2h5 rc2h4 rc2h3 rc2h2 rc2h1 rc2h0 bit symbol function 7 to 0 rc2h7 to rc2h0 reload low register bit7 to bit0 76543220 rc2l7 rc2l6 rc2l5 rc2l4 rc2l3 rc2l2 rc2l1 rc2l0 bit symbol function 7 to 0 rc2l7 to rc2l0 reload low register bit7 to bit0
hms9xc7132 / hms9xc7134 42 may.2001 ver1.1 16. ddc interface the monitor typically includes a number of user controls to set picture size, position, color balance, brightness and contrast.fur- thermore, to optimize some internal setting for different display modes, the timing characteristics should be acquired by the con- trol side. in these days, it is getting popular for these controls to go to pc host. therefore the communication between monitor and host becomes issue.ddc1, ddc2b, ddc2b+, and ddc2ab(access.bus) emerge as a standard for monitor inter- face. a transmitter clocked by incoming vsync is dedicated for ddc1 operation. an i2c interface hardware logic forms the ker- nel of ddc2b, ddc2b+, and ddc2ab. an address pointer, with post increment capability is employed to serve ddc1, ddc2b,ddc2b+ and ddc2ab modes. the conceptual block diagram is illustrated in fig. 16.1 figure 16-1 ddc interface block diagram ddc2b/ddc2ab ddc2b+ interface s1adr1 s1dat s1con s1sta sda1 scl1 ddccon vsync in intr (from s1sta) int ddcadr ddcdat x ex_ dat sw enb x ddc1 int ddc1 en swh int m0 initialization synchronization ddc1 transmitter ddc1 hold register bus clock generator shift register monitor address arbitration logic ddc1/ddc2 detection rambuf ram buffer address pointer internal bus s1adr0 7 10 monitor address
hms9xc7132 / hms9xc7134 may.2001 ver1.1 43 16.1 the special function register for ddc interface. eight sfr : s1con, s1sta, s1dat, s1adr, rambuf, ddccon, ddcadr, ddcdat. s1con, s1sta, s1dat, s1adr are just the copies of the corresponding registers in general i2c-bus interface. table 16-1 ddc mode status and ddc1 control register (ddccon : 0d7h) reset value:x00x0000b table 16-2 description of the ddccon bits 76543220 - ex_dat swenb - ddcint ddc1en swhint m0 bit symbol function 7- reserved 6 ex_dat (r/w) this bit defines the size of the edid data. it is related to the function of the post increment of the address pointer, ddcadr. when the upper limit is reached, the ddcadr will wrap around to 00h. if ex_dat is 1: the data size is 256 byte. 0: the data size is 128 byte(the addressing range for the edid data buffer is mapped from 0 to 127 ; the rest, 128 to 255 , can still be used by the system). 5 swenb (r/w) this bit indicates if the software/cpu is needed to take care of the operation of ddc1 protocol. if swenb is 1 : in ddc1 protocol, cpu is interrupted during the period of the 9th transmitting bit so that the s/w service routine can update the hold register of transmitter by moving new data from appro- priate area(it is not necessary to be the ram buffer which is pointed by ddcadr) to the register ddcdat. this transmitting must be done within 40us. 0 : the hold register of the transmitter will be automatically updated from the ram buffer without the intervention of cpu. 4- reserved 3 ddc1int (r/w) interrupt request bit. this bit is only valid in ddc1 protocol while s/w handling is enabled. this bit is set by h/w and should be cleared by s/w in interrupt service routine. 1 : interrupt request is pending. 0 : no interrupt request 2 ddc1en (r/w) ddc1 enable control bit. if ddc1en is 1 : ddc1 is enabled. 0 : ddc1 is disabled ; the activity on vsync is ignored. 1 swhint (r/w) interrupt request bit. this bit is set by h/w when ddc interface switches from ddc1 to ddc2 (i.e. the voltage transient from high to low is observed on scl1 pin). this bit should be cleared by s/w in interrupt service routine. 1 : interrupt request is pending. 0 : no interrupt request 0 m0 (r/w) ddc mode indication bit. this bit will be set by h/w when the voltage transient from high to low is observed on scl1 pin. once mode changes into ddc2 mode, the mode is reserved until pow- er is off. 0: ddc1 is set. 1: ddc2 is set.
hms9xc7132 / hms9xc7134 44 may.2001 ver1.1 ddc1 data register for transmission ( ddcdat : 0d5h) ? 8bit read and write register. ? indicates data byte to be transmitted in ddc1 proto- col. address pointer for ddc interface ( ddcadr : 0d6h) ? 8bit read and write register. ? address pointer with the capability of the post incre- ment. after each access to rambuf register(either by software or by hardware ddc1 interface), the content of this register will be increased by one. its available- both in ddc1, ddc2 (ddc2b, ddc2b+, and ddc2ab) and system operation. host type detection the detection procedure conforms to the sequences proposed by vesa monitor display data channel(ddc) specification.the monitor needs to determine the type of host system: ? ddc1 or old type host. ? ddc2b host (host is master, monitor is always slave) ? ddc2b+/ddc2ab(access.bus) host.
hms9xc7132 / hms9xc7134 may.2001 ver1.1 45 the monitor where hms9xc7132 resides is always both ddc1 and ddc2 capable with ddc2 having the higher priority. the- display shall start transmitting ddc1 signals whenever it is pow- ered on and the vertical sync signal is applied to it from the hostfor the first time. the display shall switch to ddc2 within 3 system clocks as soon as it sees a high to low transition on the clockline(scl), indicating that there are ddc2 devices connect- ed to the bus. under that condition, the mode flag, m0 will be changed from the default setting 0, to 1. accordingly, the inter- rupt will be invoked by setting flag, swhint as high. fig. 16.2 illustrates the concept and interaction between the mon- itor and the host. after power on, the ddc1en bit is set by s/w to act as a ddc1 device. therefore, the mode flag, m0, is set as 0. following vsync as clock, the monitor will transmit edid data stream to the host. however, if ddc2 clock, scl clock, is present, the monitor will be switched to ddc2b device with the mode flag setting as 1. software will judge it is a ddc2b, ddc2b+, or ddc2ab protocol. figure 16-2 host type detection is vsync present ? has a command been received ? is 2b+/a.b command detected ? is monitor ddc2b+/ddc2ab capable ? is command ddc2b command ? monitor power on communication is idle edid sent continuously using vsync as clock is ddc2 clock present ? stop sending of edid, switch to ddc2 communication mode ddc2 communication is idle. monitor is waiting for a command. respond to ddc2b command respond to ddc2b+/ ddc2ab command
hms9xc7132 / hms9xc7134 46 may.2001 ver1.1 16.2 ddc1 protocol ddc1 is primitive and a point to point interface. the monitor is always put at transmit only mode.in the initialization phase, 9 clock cycles on vsync pin will be given for the internal syn- chronization.during this period, the sda pin will be kept at high impedance state. if ddc1 hardware mode is used, the following procedure is rec- ommended to proceed ddc1 operation. step1 : reset ddc1en (by default, ddc1en is cleared as low after power on reset). step2 : set swenb as high(the default value is zero.) step3 : depending on the data size of edid data, set ex_dat as low(128 bytes) or high(256bytes). step4 : by using bulky moving commands (ddcadr, ram- buf involved) to move the entire edid data to ram buffer. step5 : reset swenb to low. step6 : reset ddcadr to 00h. step7 : set ddc1en as high. in case swenb is set as high, interrupt service routine must be finished within 40 machine cycles in 12 mhz system clock. note : if ex_dat equals to low, it is meant the lower part is oc- cupied by ddc1 operation and the upper part is still free to the system. nevertheless, the effect of the post increment just ap- plies to the part related to ddc1 operation. in other words, the system program is still able to address the lo- cations from 128 to 255 in the ram buffer through movx com- mand but without the facility of the post increment. ex) in case of accessing 200 of the ram buffer. mov r0, #200 movx a, @r0 figure 16-3 transmission protocol in ddc1 interface. 16.3 ddc2b protocol ddc2b is constructed base on philips i2c interface. however, in the level of ddc2b, pc host is fixed as the master and the mon- itor is always regarded as the slave. both master and slave can be operated as a transmitter or receiver, but the master device deter- mines which mode is activated. in this protocol, address pointer is also used. according to ddc2b specification, a0(for write mode) and a1(for read mode) are assigned as the default address of moni- tors. the reception of the incoming data in write mode or the updating of the outgoing data in read mode should be finished within the specified time limit. if software in the slave s side cannot react to the master in time, based on i2c protocol, scl pin can be stretched low to inhibit the further action from the master. the transaction can be proceeded in either byte or burst format. 1234 56789 123456 7891 b7 b6 b5 b4 b3 b2 b1 b0 hiz b7 t su(ddc1) t dov hi-z scl vclk ddc1int ddc1en sda t h(vsync) t l(vsync)
hms9xc7132 / hms9xc7134 may.2001 ver1.1 47 figure 16-4 the conceptual structure of ddc interface 16.4 ddc2ab/ddc2b+ protocol ddc2ab/ddc2b+ is a superset of ddc2b. monitors that im- plement ddc2ab/ddc2b+ are full featured access.bus de- vices. monitor that implement ddc2b+ uses the same command set as ddc2ab but cannot use access.bus device. essentially, they are similar to ddc2b. i2c interface forms the fundamental layer for both protocols. the default address for monitors is assigned as 6eh other than a0/a1h in ddc2b. monitors and hosts can play both the roles of master and slave. under this kind of protocol, it is easy to extend the support for hosts to read vdif(vesa video display information format) and remotely control monitor functions. command / information sequence between host and monitor must conform to the specification of access.bus. timing rules specified in access.bus such as maximum response time to reset message(< 250 ms)form host, maximum time to hold scl low(< 2ms) etc. can be satisfied through software check and built-in timers such as timer0, timer1. in ddc2ab/ddc2b+, monitor itself can act as a monitor to ac- tivate the transaction. the default address assigned for host is 50h. ddc interrupt vector address ( 003bh ) ddc2b+/ddc2ab utilities ddc2b utilities ddc1 utilities check mode flag in ddccon mode = 1 mode = 1 mode = 0 i2c service routines i2c interface (h/w) ddc1 transmitter (h/w) ddc2b+/ddc2ab command received ddc2b command received swenb = 1 swenb = 0
hms9xc7132 / hms9xc7134 48 may.2001 ver1.1 16.5 the ram buffer and ddc application ram buffer (rambuf) : the ram buffer can be shared as the system ram or ddc ram buffer. table 16-3 description of the ex_dat and swenb note 1. read/write through movx instruction might conflict with the access from ddc1 hardware. so, the access from cpu by using movx instruction is forbidden. 2. read/write through ddcadr and rambuf registers has the conflicting problem also. even the content of ddcadr, which should be employed by ddc1 hardware, will be damaged. so, it is inhibited to use this type of access. 3. if ddcadr reaches 127, it will automatically wrap around to 0 after the access is done. 4. if ddcadr reaches 255, it will automatically wrap around to 0 after the access is done. 5. the access conflicting can be avoided because ddc1 access is done by the interrupt service routine. however, the edid transferring from the ram buffer should be finished within 40 us. mode ex_dat 0 swenb 0 ddc1 xram : 0 to 127 xram : 128 to 255 normally reserved for ddc1 edid data (note 1, note 2, note 3) available for the system access. (note 2) 1 0 normally reserved for ddc1 edid data (note 1, note 2) normally reserved for ddc1 edid data. (note 1, note 2, note 4) 0 1 normally reserved for ddc1 edid data (note 3, note 5) available for the system access. 1 1 normally reserved for ddc1 edid data (note 5) normally reserved for ddc1 edid data. (note 4, note 5) 0 1 normally reserved for ddc2 edid data (note 3) available for the system access. 1 1 normally reserved for ddc2 edid data normally reserved for ddc2 edid data. (note 4) ddc2
hms9xc7132 / hms9xc7134 may.2001 ver1.1 49 example program; ddc interface initial & interrupt part initial: mov ddccon,#01h ; swenb(0) mov ddcadr,#0 ; mov ddccon,#00100100b ; 128(6),ddc1_int(5),ddc1_enable(1) mov s1con,#47h ; 100khz(011),eni1(1),ack_enable(1) mov s1adr0, #0a1h ; ddc2b slave address mov s1adr1, #41h ; factory alignment host ;================================================================= ; ddc interface ; 1. isr s1sta
s1dat . ; 2. isr s1con refresh . ; 3. slaver receive address match ! " s1dat
# s1sta ; dummy data
writing $ . % slave receive &' . ;================================================================= ; task : ddc interrupt service ; input : control & status peripheral register ;================================================================= ddc_header: db 00,0ffh,0ffh,0ffh,0ffh,0ffh,0ffh,00 ddc_isr: push psw ; push dph ; push dpl ; push acc ; push 00 ; push 01 ; mov a, ddccon ; anl a, #00001000b ; (1) ddc1int request(bit3=1)? jz ddc2_svc ; ;===================================================== ddc1_mode: mov a, miicflag ; anl a,#00000011b ;busersoftddc(1), bddc1enable(0) cjne a, #03h, ddc1enable ; mov a, #0ffh ; mov ddcdat, a ; ljmp ddc_int_end ; ddc1enable: mov a, mddcdata ; mov ddcdat, a ; mov a, mddcaddress ; cjne a, #80h, ddc1_svc ; mov ddccon, #01h ; ddc1 disable,ddc2 mode ddc1_svc: clr c ; subb a, #8 ; jnc normalddc1 ; mov dptr, #ddc_header ; mov a, r0 ; movc a, @a+dptr ; sjmp ddc1_save ; normalddc1: mov a, #edid_data ; add a, r0 ; data post mov r0, a ; movx a, @r0 ; ddc1_save: mov ddcdat, a ; inc mddcaddress ; ljmp ddc_int_end ; ;===================================================== ddc2_svc: mov a, ddccon ; anl a, #00000010b ; (2) swhint (scllow bit1=1) scl activity ? jz ddc_i2c_svc ; mov mddcaddress, #00h ; ddc1 disable,ddc2 mode mov ddccon, #00000001b ; ddc_i2c_svc: mov a, s1sta ; (3) i2c abnormal by g-call,stop, arbitration and no acknowledge mov mi2c_status,a ; anl a, #11000110b ; 1 1 0 0 0 1 1 0 jnz ddc_abnormal ; gc,stop,intr,tx_mode,busy,blost,/ack_rep,slv mov a, s1con ; anl a, #00001000b ; (4) host address matched ? jnz addr_match ; ljmp ddc2b_svc ; (5) 1 byte data access by ddc2b format addr_match: mov ddccon, #01h ; ddc1 disable,ddc2 mode setb bi2c_dir ; tx mov a, s1dat ; anl a, #0feh ; lsb bit masking cjne a, #60h, ddc2b_mode ; 60h = factory host ?
hms9xc7132 / hms9xc7134 50 may.2001 ver1.1 factory_mode: setb bfactorymode ; factory alignment host matched 40h setb bservice ; mov a, mi2c_status ; anl a, #10h ; jz align_add_rx ; slave receive command ljmp align_i2c_tx ; slave transmit command align_add_rx: clr bi2c_dir ; rx mcu <== host mov a, #0 ; mov miicbuffer+psave, a ; mov miicbuffer+pread, a ; mov s1dat,#0ffh ; dummy write mov s1con, #01000111b ; i2c enable, ack out when own slave address in ljmp ddc_int_end ; factory slave receive start ddc2b_mode: clr bfactorymode ; factory alignment host matched cjne a, #0a0h, ddc_abnormal; a0h = ddc2b host ? mov a, mi2c_status ; anl a, #10h ; jnz ddc_i2c_tx ; slave transmit clr bi2c_dir ; mov s1dat,#0ffh ; dummy write mov s1con, #01000111b ; i2c enable, ack out when own slave address in ljmp ddc_int_end ; ddc slave receive start ;===================================================== ddc2b_svc: ; 1 byte data handling jb bfactorymode,line_svc ; mov a, mi2c_status ; anl a, #10h ; jnz ddc_i2c_tx ; slave transmit ; ddc_i2c_rx: mov a, s1dat ; slave-receive mov mddcaddress, a ; subaddress catch sjmp ddc_i2c_ref ; ddc_i2c_tx: mov a, mddcaddress ; slave transmit anl a, #7fh ; mov r0,a ; clr c ; subb a, #8 ; mov a, r0 ; jnc tx_mode_svc ; mov dptr, #ddc_header ; header load movc a, @a+dptr ; sjmp tx_mode_out ; tx_mode_svc: add a, #edid_data ; 0x80~0xff mov r0, a ; movx a, @r0 ; tx_mode_out: mov s1dat, a ; edid data store at s1dat inc mddcaddress ; mov s1con, #47h ; clear addr(bit3)11-15 edit mov ni2c_abn_cnt,#80h ; no ack within 128 msec, p1sfs.1=port sjmp ddc_int_end ; ===================================================== ddc_abnormal: mov s1con, #00000111b ; i2c enable, stop out, ack out mov ni2c_abn_cnt,#0 ; initial hangup check counter mov p1sfs,#00001111b ; normal i2c hardware interface clr bfactorymode ; mov ddccon,#01h ; swenb(0) mov ddcadr,#0 ; mov ddccon,#00100100b ; 128(6),ddc1_int(5),ddc1_enable(1) mov s1con,#47h ; 100khz(011),eni1(1),ack_enable(1) mov s1adr0, #0a1h ; ddc2b slave address mov s1adr1, #41h ; factory alignment host jnz ddc_i2c_stx ; ddc_i2c_srx: ; mov a,s1dat ; receive sjmp ddc_i2c_ref ; ddc_i2c_stx: ; mov s1dat,#0ffh ; transmit ddc_i2c_ref: ; mov s1con, #01000111b ; i2c enable, ack out when own slave address in ;------------------------------------ ddc_int_end: pop 01 ; pop 00 ; pop acc ; pop dpl ; pop dph ; pop psw ; reti ; ;------------------------------------
hms9xc7132 / hms9xc7134 may.2001 ver1.1 51 17. i2c interface in the monitor mcu are two i2c interfaces implemented. ? the first one is used by the ddc protocols. ? the second one is dedicated for internal connection. with this one it s possible to control the video, deflection, conver- gence and some other functions of the monitor. the serial port supports the twin line i2c-bus, consists of a data line(sdax) and a clock line(sclx). ? sda1, scl1 : the serial port line for ddc protocol ? sda2, scl2 : the serial port line for internal connection in both i2c interfaces, these lines also function as i/o port lines as follows. ? sda1 / p1.1, scl1 / p1.0, sda2 / p1.7, scl2 / p1.6 the system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. the i2c serial i/o has complete autonomy in byte handling and operates in 4 modes. ? master transmitter ? master receiver ? slave transmitter ? slave receiver these functions are controlled by the sfrs. ? sxcon : the control of byte handling and the operation of 4 mode. ? sxsta : the contents of its register may also be used as a vector to various service routines. ? sxdat : data shift register. ? sxadr : slave address register. slave address recognition is performed by on-chip h/w. figure 17-1 the block diagram of the i2c-bus serial i/o. slave address shift register arbitration + sync. logic bus clock generation control register status register internal bus sdax sclx - 7 0 0 0 0 7 7 7
hms9xc7132 / hms9xc7134 52 may.2001 ver1.1 17.1 the special function register for i 2 c interface. serial control register(sxcon; s1con, s2con) table 17-1 serial control register(sxcon; s1con : 0d8h , s2con : 0dch) table 17-2 description of the sxcon bits table 17-3 selection of the serial clock frequency scl in master mode of operation. 76543210 cr2 eni1 sta sto addr aa cr1 cr0 bit 7 symbol cr2 function this bit along with bits cr1and cr0 determines the serial clock frequency when sio is in the master mode. 6 eni1 enable iic. when eni1 = 0, the iic is disabled. sda and scl outputs are in the high impedance state. 5 sta start flag. when this bit is set, the sio h/w checks the status of the i2c-bus and generates a start condition if the bus free. if the bus is busy, the sio will generate a repeated start condition when this bit is set. 4 sto stop flag. with this bit set while in master mode a stop condition is generated. when a stop condition is detected on the i2c-bus, the sio hardware clears the sto flag. 3 addr this bit is set when address byte was received. must be cleared by software. 2 aa acknowledge enable signal. if this bit is set, an acknowledge(low level to sda)is returned during the acknowledge clock pulse on the scl line when : ?own slave address is received ?a data byte is received while the device is programmed to be a master receiver ?a data byte is received while the device is a selected slave receiver. when this bit is reset, no acknowledge is returned. sio release sda line as high during the acknowledge clock pulse. 0 cr0 these two bits along with the cr2 bit determine the serial clock frequency when sio is in the master mode. 1 cr1 cr2 cr1 f osc divisor bit rate (khz) at f osc 0 0 16 250 375 - 8mhz 12mhz 16mhz cr0 0 0 0 14 285.71 428.57 - 1 0 1 40 100 150 - 0 0 1 60 66.67 100 - 1 1 0 120 33.33 50 - 0
hms9xc7132 / hms9xc7134 may.2001 ver1.1 53 serial status register(sxsta) sxsta is a read-only register. the contents of this register may be used as a vector to a service routine. this optimize d the response time of the software and consequently that of the i2c-bus. the status codes for all possible modes of the i2c-bus inter face are given table table 17-4 serial status register (sxsta; s1sta:0d9h, s2sta:0ddh) table 17-5 description of sxsta data shift register(sxdat; s1dat, s2dat) sxdat contains the serial data to be transmitted or data which has just been received. the msb (bit7) is transmitted or received first; i,e. data shifted from right to left. table 17-6 serial data shift register addressing register(sxadr) this 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receive/ transmitter. table 17-7 address register(sla6 to sla0 : own slave address.) 76543210 gc stop intr tx_mode bbusy blost /ack_rep slv bit 7 symbol gc function general call flag. 6 stop stop flag. this bit is set when a stop condition was received. 5 intr bus busy state flag. this bit is set when the bus is being used by another master. otherwise, this bit is reset. interrupt flag. this bit is set when a sio interrupt is requested. 4 tx_mode transmission mode flag. this bit is set when the sio is a transmitter. otherwise, this bit is reset. bus lost flag. this bit is set when the master loses the bus contention. otherwise, this bit is reset. 1 /ack_rep acknowledge response flag. this bit is set when the receiver transmits the not acknowledge signal. this bit is reset when the receiver transmits the acknowledge signal. slave mode flag. this bit is set when the sio plays role in the slave mode. otherwise, this bit is reset. blost 2 slv 0 bbusy 3 76543210 sxdat7 sxdat6 sxdat5 sxdat4 sxdat3 sxdat2 sxdat1 sxdat0 76543210 sla6 sla5 sla4 sla3 sla2 sla1 sla0 -
hms9xc7132 / hms9xc7134 54 may.2001 ver1.1 17.2 programmers guide for i2c and ddc2 the i2c serial i/o and ddc interface has operates in 4 modes. ? master transmitter ? master receiver ? slave transmitter ? slave receiver 17.2.1 master transmitter mode slave transmitter mode 1. read sxsta. 2. if bbusy == 1 then go to step1. else then write slave address to sxdat and set both eni and sta, reset aa in sxcon. 3. wait for interrupt. 4. read sxsta. if blost == 1 or /ack_rep == 1* then write dummy data to sxdat. go to step1. else then clear sta. 5. perform required service routines. if this datum == last then set sto in sxcon and write last data to sxdat**. go to step 6. else then write next data to sxdat**. go to step3. 6. wait for interrupt. write dummy data to sxdat**. * : 1. if the master dont receive the acknowledge from the slave, it generates the stop condition and returns to the idle sta te. **: 1. this action should be the last in service routine. 1. write slave address to sxadr, set aa and eni in sxcon. 2. wait for interrupt. 3. read sxsta and write the first data to sxdat*. reset aa in sxcon. 5. wait for interrupt. 6. read sxsta. if /ack_rep == 1** then go to step7. else then write the next sxdat*. go to step5. 7. write dummy data to sxdat*. * : 1. these actions should be the last. **: 1. if the master want to stop the current data requests, it dont have to acknowledge to the slave transmitter. 2. if the slave dont receive the acknowledge from the master, it releases the sda and enters the idle state, so if the master is to resume the data requests, it must regenerate the start condition.
hms9xc7132 / hms9xc7134 may.2001 ver1.1 55 master receiver mode slave transmitter mode 1. read sxsta. 2. if bbusy == 1 then go to step1. else then write slave address to sxdat and set both eni1 and sta, reset aa in sxcon. 3. wait for interrupt. 4. read sxsta. if blost == 1 or /ack_rep == 1 then write dummy data to sxdat go to step1. else then clear sta and write ffh to sxdat. set aa in sxcon. 5. wait for interrupt. 6. read sxsta. if this datum == last then reset aa* and read sxdat**. go to step7. else then read sxdat**. go to step5. 7. wait for interrupt. read sxsta. read sxdat**. * : 1. if the master want to terminate the current data requests, it dont have to acknowledge to the slave. **: 1. this action should be the last. 1. write slave address to sxadr, set aa and eni in sxcon. 2. wait for interrupt. 3. read sxsta and write ffh to sxdat*. 5. wait for interrupt. 6. read sxsta. if stop == 1 then go to step7. else then read data from sxdat*. go to step5. 7. read dummy data from sxdat*. * : 1. this action should be the last.
hms9xc7132 / hms9xc7134 56 may.2001 ver1.1 master : restart (transmitter) 1. read sxsta. 2. if bbusy == 1 then go to step1. else then write slave address to sxdat and set both eni1 and sta in sxcon. reset aa in sxcon. 3. wait for interrupt. 4. read sxsta. if blost == 1 or /ack_rep == 1 then write dummy data to sxdat. go to step1. else then clear sta. 5. perform required service routines. if this datum == last then if restart is required then set sta in sxcon and write last data to sxdat*. go to step6. else then set sto in sxcon and write last data to sxdat*. go to step7. else then write next data to sxdat*. go to step3. 6. wait for interrupt. write slave address to sxdat*. go to step3. 7. wait for interrupt. write dummy data to sxdat*. * : 1. this action should be the last in service routine.
hms9xc7132 / hms9xc7134 may.2001 ver1.1 57 18. pulse width modulation 18.1 static pwm there are eight static pwm in the hms9xc7132. these channels provide output pulses of programmable duty cy- cle and polarity. the duty cycle is defined by a counter. the 8-bit counter of a pwm counts modulo 256, i.e. from 0 to 255 inclusive. the value held in the 8-bit counter is compared to the contents of the special function register(pwmn) of the cor- responding pwm. the polarity of the pwm outputs is program- mable and selected by the pwmlvl bit in pwmcon register. provided the contents of a pwmn register is equal to or greater than the counter value, the corresponding pwm output is set high (with pwmlvl =0). if the contents of this register is less than the counter value, the corresponding pwm output is set low(with pwmlvl =0). the pulse-width-ratio is therefore defined by the contents of the corresponding special function register(pwmn) of a pwm. by loading the corresponding spe- cial function register(pwmn) with either 00h or ffh, the pwm output can be retained at a constant high or low level respectively(with pwmlvl = 0). the pwm outputs pwm0 to pwm7 register share the same pins as port2.2~port2.7, port3.4 and port3.5 respectively. selection of the pin function as either a pwm output, a port line or the other function is achieved by using the appropriate value of p2sf register. the repetition frequency (fpwm) at a pwm output is given by: fpwm = fosc / (2 x 256) table 18-1 pwm control register (pwmcon : 0a1h) table 18-2 description of the pwmcon bits 76543210 pwmlvl pwm6cfg pwm5cfg pwm4cfg pwm3cfg pwm2cfg pwm1cfg pwm0cfg bit symbol function 7 pwmlvl polarity selection of the pwms. 0 : pwm outputs are not inverted. 1 : pwm outputs are inverted. 6 to 0 pwm6cfg to pwm0cfg output type selection of the pwms. 0 : open-drain type. 1 : push-pull type
hms9xc7132 / hms9xc7134 58 may.2001 ver1.1 18.2 dynamic pwm there are two dynamic pwms in the hms9xc7132. the dp- wms can be used to generate various waveform by software pro- gramming, and are used to achieve geometric compensation by generating a parabola output waveform which is synchronized with vsyncin signal for pin/trap, bow/tilt, vertical linearity or focus compensation in monitor system. this is achieved by utilizing timer2. the low 8-bit in timer2 is used as 8-bit counter for pwm signal and the high 8-bit in timer2 is used to decide the number of pwms in one video frame. one video frame can be divided to any number of blocks according to the register rc2h value within 256 blocks, and here the rc2l will be 00h for 8-bit pwm resolution. the dynamic pwm outputs dpwm0 to dpwm1 register share the same pins as port2.0~port2.1respectively. the repetition frequency (fdpwm) at a dpwm output is given by (in case of rc2l=00h): fdpwm = fosc / (2 x 256) table 18-3 dynamic pwm control register (dpwmcon : 0b1h) table 18-4 description of the dpwmcon bits table 18-5 dpwm application circuit 76543210 dpwmlvl - - - - - dpwm1cfg dpwm0cfg bit symbol function 7 dpwmlvl polarity selection of the dpwms. 0 : dpwm outputs are not inverted. 1 : dpwm outputs are inverted. 1 to 0 dpwm1cfg to dpwm0cfg output type selection of the dpwms. 0 : open-drain type. 1 : push-pull type dpwmx vsync vdd
hms9xc7132 / hms9xc7134 may.2001 ver1.1 59 using one dynamic pwm to compensate the following h size distortion : using one dynamic pwm to compensate the following h center distortion : 1. pincushion (pcc amplitude) 2. trapezoid (keystone) 3. cbow (quarter width) 4. pcc corner 5. s curve 1. pin balance (bow) 2. key balance (tilt) 3. corner balance
hms9xc7132 / hms9xc7134 60 may.2001 ver1.1 19. sync processor the characteristics of sync processor are as follows. automatic mode detection by hardware to capture the following signal characteristics : ? hsync and vsync frequency measured with 12-bit accuracy (fsh= 12mhz, fsv= 125khz) ? hsync and vsync polarity ? hsync and vsync presence needed for implementing the vesa dpms standard integrated composite sync separation integrated signal generators for generating : ? free running horizontal and vertical sync pulses ? clamping pulse(back porch, front porch) ? pattern signal (white picture, black picture, cross hatch and inverse cross hatch) special option : ? missing sync pulse insertion all measured parameters are stored in special function register such that the data is available at any time. the block diagram of the complete sync processor is given in figure 19-1 19.1 sync input signals the sync inputs are able to handle standard ttl level sync sig- nals. from figure 19-1 it can be seen that both the hsyncin and sogin inputs accept composite sync signals. the hsyncin and vsyncin input is meant to be connected to the hsync and vsync of the vga cable while sogin input is meant to be connected to a sync slicer in order to handle sync-on-green at the video input. this last signal should have a ttl level also. the selection be- tween the hsyncin and the sogin inputs, as well as the selec- tion between the vsyncin and separated vsync, can be done via software. table 19-1 sync input selection 19.2 horizontal polarity correction in order to simplify the processing in the following stages, the hsync polarity correction circuit is able to convert the input sync signals to positive polarity signals in all situations. this cor- rection is achieved by the aid of hpol and hp. hpol and hp are only settled down in several horizontal scan- ning lines or a few milliseconds after power-on or timing mode change. 19.3 vertical polarity correction the purpose of the vertical polarity correction is similar to the horizontal polarity correction. to get the correct resultafter pow- er-on or a timing mode change, at least 5 frames is needed. 19.4 vertical sync separation this block separates the vertical sync from a composite sync sig- nal. at approximately 1/4 of each hsync line the logical level is latched. this yields a slightly delayed vertical sync signal. special precautions have been taken to suppress equalizing puls- es when present and to allow both polarities of the composite sig- nal.the format of the composite sync signal can be standard, as given in figure 19-2, or can be one of the non standard format as given in figure 19-3 select flag hsel signal to detector 0 : hsyncin 1 : sogin vsel 0 : vsyncin 1 : separated vsync
hms9xc7132 / hms9xc7134 may.2001 ver1.1 61 figure 19-1 block diagram of sync processor capture sfr control sfr 1 / 96 f sh f sv f osc hp vp hpol vpol hpres vpres hsync change vsync change cpu mdint cpu hf vf control vint mux xor sync sep hsync detection hsync generator vsync detection vsync generator mux/ clmp v h hp hsyncout clamp vsyncout hp hpol hpres vp vpol vpres hp hf hopol hpg hopw vp vf vopol vpg vopw hsel vsel hsyncin sogin vsyncin hpol vpol patout pat mux mux xor
hms9xc7132 / hms9xc7134 62 may.2001 ver1.1 19.5 horizontal sync. detection this block extracts the following parameters from the incoming horizontal or composite sync : ? hper : the number of clock cycles (fsh = 12mhz) be- tween five sync pulses (4 period time), thus the 12 bits val- ue hper will be equal to ((4 x 12 x 106 / fh) - 1) where fh is the horizontal sync frequency in hz. ? hpol : the polarity of the sync signal, hpol will be reset in case of a positive polarity and set in case of a negative polarity. the 1/4 point value of hsync period time will be latched for hpol. ? hpres :to detect the presence of the valid hsync sig- nal, detector measures the time interval between five sync pulses (4 period time). no active sync is coming in if the counter reaches a value of ff0h(4080). ? hchg : the hchg flag will be set if a change is detected in either the polarity or the period time. to avoid unintended setting of the hchg flag a small deviation in the period time is allowed.the allowed deviation is approximately 167ns per line. 19.6 vertical sync. detection this block extracts the following parameters from the incoming vertical sync: ? vper : either the number of clock cycles (fsv=125khz sampling) between two sync pulses(period time). in case the period time is measured this 12 bits vper will be equal to 125 x 103 / fv where fv is the vertical sync frequency in hz. ? vpol : the polarity of the sync signal, vpol will be reset in case of a positive polarity and reset in case of a negative polarity. it should be noted here that in case of a composite sync signal at the input the parameter vpol will be set al- ways, disregarding the polarity of the incoming composite sync. the 1/4 value of incoming vsync value will be latched for vpol. ? vpres : to detect the presence of the valid vsync sig- nal, detector measures the time interval between two con- secutive rising edges of the input signal. no active sync is coming in if the counter reaches a value of ff0h(4080). ? vchg : the vchg flag will be set if a c hange is detected in either the polarity or the period time. to avoid unintended setting of the vchg flag a small deviation in the period time is allowed.the allowed deviation is approximately 32us per line. table 19-2 threshold frequencies of the presence detector detection input threshold frequency hsync input 12 khz vsync input 30 hz
hms9xc7132 / hms9xc7134 may.2001 ver1.1 63 figure 19-2 standard composite sync signals figure 19-3 non-standard composite sync signals csync hsync vsync 2nd field 1st field csync hsync vsync 1st field 2nd field hsync vsync csync-1 csync-2 csync-3 csync-4 csync-5 csync-6
hms9xc7132 / hms9xc7134 64 may.2001 ver1.1 both the hchg and the vchg signals are combined and con- nected to the internal interrupt. interrupt will be issued when change is continuously detected like following table. due to this fast interrupt the s-correction can be set to a safe level before any damage to the deflection circuitry will occur. table 19-3 time interval between mode change and interrupt internally there are two 12-bit counter for hsync and vsync period check , hsync counter count up from 0 to 4096 for 4 hsync lines according to 12mhz clock, and vsync counter count up from 0 to 4096 for one vsync line according to 125khz clock. for hsync static state that hsync frequency is under 12khz, counter value is more than 4080 value,and for vsync static state that vsync frequency is under 32hz, counter value is more than 4080 value. hsync hpnew < hppre hpnew x 61 to (4 x hpnew x 15) - (n x hppre) hpnew > hppre (4 x hpnew) x 3 - (n x hppre) pos => neg 60 hsync lines neg => pos 60 hsync lines vsync period period polarity polarity vpnew < vppre (vpnew x 2 + vpprev) to (vnew x 3) vpnew > vppre (vpnew) to (vpnew x 2) pos => neg 3 vsync lines neg => pos 2 vsync lines mode change interval between mode change and interrupt to static state (4 x hpnew) x 3 - (n x hppre) to static state (vpnew) to (vpnew x 2)
hms9xc7132 / hms9xc7134 may.2001 ver1.1 65 19.7 horizontal sync. generator this block generates horizontal sync pulses with positive polari- ty.this can be done in 3 modes, selectable with hpg. when hpg is 00, the generator operates in the free running mode and the gen- erated pulse repetition period equals hf x 1/12 mhz clock peri- od, where hf is a 10 bit value. as a result the frequency of the free running output sync pulse equals 12 x 106 / hf, with about 12 khz as lower boundary.when hpg is 01, the input sync pulse is followed and a substitution pulse is inserted. in case hpg equals 11, the inputsync pulse is followed but a substitution pulse is disabled, while the incoming sync is missing. table 19-4 modes of the horizontal pulse generator table 19-5 free running horizontal sync pulse width example program; freerun mode hpg[1:0] selected mode 0 0 free running mode period time of horizontal pulse generator (= hf) 0 1 the same pulse as the input horizontal sync substitution pulse insertion in case of a missing sync pulse 1 0 reserved 1 1 the same pulse as the input horizontal sync no substitution pulse insertion in case of a missing sync pulse hopw[4:0] selected mode 00000 2 x 83 ns 00001 3 x 83 ns 00010 4 x 83 ns ------- incremented by 83ns (1/12 x 10 -6 ) 11101 31 x 83 ns 11110 32 x 83 ns 11111 33 x 83 ns ;================================================================ ; free running ;================================================================ setfreerunning: lcall setvcp setfreerunning1: mov a, #01000100b ; rising edge interrupt mov mdcon, a ; mov hfh,#00101110b ; hf = 64.6 khz mov hfl,#01010000b ; hopw[10000] mov vfh,#01000010b ; vf = 60 hz mov vfl,#11001000b ; vopw[1000] mov cpgen,#11100000b ; white picture clamping and pattern mov a, #01000000b ; negative hsync, positive vsync free-run mov hvgen, a ; lcall dpmshlinearity ; ret
hms9xc7132 / hms9xc7134 66 may.2001 ver1.1 19.8 vertical sync. generator this block generates vertical sync pulses with positive polarity. this can be done in 3 modes, selectable with vpg. when vpg is 00, the generator operates in the free running mode and the gen- erated pulse repetition period equals vf x hf x 1/12 mhz clock period, where vf is a 12 bit value. as a result the frequency of the free running output sync pulse equals 12 x 106 / hf / vf. when vpg is 01, the input sync pulse is followed and a substitu- tion pulse is inserted. in case vpg equals 11, the input sync pulse is followed but a substitution pulse is disabled, while the incom- ing sync is missing. table 19-6 modes of the vertical pulse generator table 19-7 free running vertical sync pulse width 19.9 hsync / vsync output driver this is output stage for hsyncout and vsyncout. it offers out- put selection, output enabling/disabling and output polarity selec- tion. with hopol and vopol the output is selected. vpg[1:0] selected mode 0 0 free running mode period time of vertical pulse generator (= vf) 0 1 the same pulse as the input horizontal sync substitution pulse insertion in case of a missing sync pulse 1 0 reserved 1 1 the same pulse as the input vertical sync no substitution pulse insertion in case of a missing sync pulse vopw[3:0] selected mode 0000 2 x t h(free) 0001 3 x t h(free) 0010 4 x t h(free) ------- incremented by t h(free) 1101 15 x t h(free) 1110 16 x t h(free) 1111 17 x t h(free)
hms9xc7132 / hms9xc7134 may.2001 ver1.1 67 19.10 clamp pulse generator the clamp pulse is generated by setting clmpen and always ac- companies the hsyncout pulse, even in the free running mode. this block generates a clamping pulse with programmable pulse width, determined by cpw. it can be started at the front porch (cfb reset) or at the back porch (cfb set), and the polarity can be set with copol. table 19-8 clamping pulse width 19.11 pattern generator this generator is used for test pattern generation when in free run- ning mode.four picture can be selected : a white, a cross hatch, a balck and inverted cross hatch pictures.when not in free running mode , the output is disabled. the pattern output can be used for burn-in test or e.g. for quick servicing without the need of a video source. the displayed pattern might look different in the different timing modes,symmetric display is not guaranteed. 19.12 suspend mode the complete sync processor can be set into a suspend mode for lowering the power consumption by means of signal mddn. table 19-9 suspend mode table 19-10 mode detection control register.(mdcon : 0f1h) cpw[2:0] clamping pulse width 000(11) 5 x 83ns 001(11) 9 x 83ns 010(11) 13 x 83ns 011(11) 17 x 83ns 100(11) 21 x 83ns 101(11) 25 x 83ns 110(11) 29 x 83ns 111(11) 33 x 83ns mddn mode 0 sync. processor is running.(default) 1 sync. processor is disabled. 76543210 mddn clmpen paten - - vinte hsel vsel
hms9xc7132 / hms9xc7134 68 may.2001 ver1.1 table 19-11 description of the mdcon bits table 19-12 mode detection status register(mdst : 0f2h) table 19-13 description of the mdst bits bit symbol function 7 mddn 0 : hardware mode detection operating normally(default) 1 : hardware mode detection disabled (low power consumption) 4 to 3 - not used 1 hsel 0 : vsyncin 1 : separated vsync 0 vsel 0 : hsyncin 1 : sogin 2 vinte vsync rising or falling edge interrupt select 0: vsync rising edge interrupt 1: vsync falling edge interrupt 6 clmpen 0 : clamp pulse out disabled(default) 1 : clamp pulse out enabled 5 paten 0 : pattern out disabled(default) 1 : pattern out enabled 76543210 - vint hpres vpres hpol vpol hchg vchg bit symbol function 5 hpres indicate the presence of hsync 0 : not present (hfreq < 12 khz) 1 : present ( hfreq 3 12 khz) 4 vpres indicate the presence of vsync 0 : not present (vfreq < 30 hz) 1 : present ( vfreq 3 30 hz) 3 hpol indicate the polarity of hsync/csync : 0 : positive polarity 1 : negative polarity 2 vpol indicate the polarity of vsync : 0 : positive polarity 1 : negative polarity 6 vint vsync interrupt flag 7 - not used 1 hchg indicate a change in horizontal period and/or polarity: 0 : no change 1 : change detected 0 vchg indicate a change in vertical period and/or polarity: 0 : no change 1 : change detected
hms9xc7132 / hms9xc7134 may.2001 ver1.1 69 table 19-14 vsync period low byte register (vph : 0f3h) table 19-15 hsync period low byte register (hph : 0f4h) table 19-16 vsync and hsync period low high register (vhpl : 0f5h) table 19-17 hsync and vsync generation control register.(hvgen : 0f9h) table 19-18 description of the hvgen bits 76543210 vp11 vp10 vp9 vp8 vp7 vp6 vp5 vp4 76543210 hp11 hp10 hp9 hp8 hp7 hp6 hp5 hp4 76543210 vp3 vp2 vp1 vp0 hp3 hp2 hp1 hp0 76543210 - hopol hpg1 hpg0 - vopol vpg1 vpg0 bit symbol function 6 hopol select polarity of the horizontal output pulse 0 : positive polarity 1 : negative polarity 7 - not used 5 to 4 hpg1 to hpg0 horizontal pulse output modes 00 : free running 01 : missing insertion 10 : reserved 11 : the same pulse as the incoming horizontal sync. 2 vopol select polarity of the vertical output pulse 0 : positive polarity 1 : negative polarity 1 to 0 vpg1 to vpg0 vertical pulse output modes 00 : free running 01 : missing insertion 10 : reserved 11 : the same pulse as the incoming vertical sync. 3 - not used
hms9xc7132 / hms9xc7134 70 may.2001 ver1.1 table 19-19 vsync free running output high byte register (vfh : 0fbh) table 19-20 vsync free running output low byte register (vfl : 0fch) table 19-21 hsync free running output high byte register (hfh : 0fdh) table 19-22 hsync free running output low byte register (hfl : 0feh) table 19-23 clamping and pattern control register(cpgen : 0fah) table 19-24 description of the cpgen bits 76543210 vf11 vf10 vf9 vf8 vf7 vf6 vf5 vf4 76543210 vf3 vf2 vf1 vf0 vopw3 vopw2 vopw1 vopw0 76543210 hf9 hf8 hf7 hf6 hf5 hf4 hf3 hf2 76543210 hf1 hf0 - hopw4 hopw3 hopw2 hopw1 hopw0 76543210 copol cfb cpw2 cpw1 cpw0 - pats1 pats0 bit symbol function 7 copol select the polarity or level of the clamping pulse: 0 : positive polarity when enabled, static low level when disabled 1 : negative polarity when enabled, static high level when disabled 6 cfb select the trigger moment of the clamping output pulse : 0 : clamp pulse after front porch of horizontal sync 1 : clamp pulse after back porch of horizontal sync 5 to 3 cpw2 to cpw0 clamp pulse width 1 to 0 pats1 to pats0 select one of the following patterns : 00 : white picture 01 : cross hatch picture 10 : black picture 11 : inverse cross hatch picture 2 - not used
hms9xc7132 / hms9xc7134 may.2001 ver1.1 71 20. analog-to-digital convertor (adc) the analog to digital converter (a/d) allows conversion of an an- alog input to a corresponding 8-bit digital value. thea/d module has four analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which generates the result via successive approxima- tion. the analog supply voltage is connected to vdd2 of ladder resistance of a/d module. the a/d module has two registers which are the control register acon and a/d result register adat. the register acon, shown in table 17.1, controls the operation of the a/d converter module. to use analog inputs, i/o is selected by p1sfs register. the processing of conversion starts when the start bit adst is set to 1. after one cycle, it is cleared by hardware. the register adat contains the results of the a/d conversion. when conver- sion is completed, the result is loaded into the adat the a/d conversion status bit adsf is set to 1. the block diagram of the a/d module is shown in fig. 17.1. the a/d status bit adsf is set automatically when a/d conversion is completed, cleared when a/d conversion is in process. the con- version time takes maximum 13us (@12mhz) figure 20-1 a/d block diagram input mux ach0 ach1 ach2 ach3 acon internal bus adat vdd2 ladder resistor decoder s/h successive approximation circuit
hms9xc7132 / hms9xc7134 72 may.2001 ver1.1 table 20-1 adc control register (acon : 97h) table 20-2 description of the acon bits table 20-3 adc data register (adat : 96h) table 20-4 description of the adat bits 76543210 - - aden - ads1 ads0 adst adsf bit symbol function 7 to 6 - reserved 5 aden adc enable bit 0 : adc shut off and consumes no operating current 1 : enable adc 4 - reserved 3 to 2 ads1, ads0 0, 0 0, 1 1, 0 1, 1 analog channel select channel0 (ach0) channel1 (ach1) channel2 (ach2) channel3 (ach3) 1 adst adc start bit 0 : force to zero 1 : start an adc; after one cycle, bit is cleared to 0 0 adsf adc status bit 0 : a/d conversion is in process 1 : a/d conversion is completed, not in process 76543210 adat7 adat6 adat5 adat4 adat3 adat2 adat1 adat0 bit symbol function 7 to 6 adat7 to adat0 a/d conversion result bit7 to bit0
hms9xc7132 / hms9xc7134 may.2001 ver1.1 73 21. operation mode 21.1 otp mode the hms97c7132 is programmed by using a modified quick- pulse programming algorithm. the hms97c7132 contains two signature bytes that can be read and used by an eprom program- ming system to identify the device. the signature bytes identify the device as an manufactured by hme. table 21-1 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. the circuit configuration and waveforms for quick pulse pro- gramming are shown in figure 21-1 and figure 21-2. figure 21- 3 shows the circuit configuration for normal program memory verification. ?program / verify algorithms any algorithm in agreement with the conditions listed in table 21-1, and which satisfies the timing specifications is suitable. table 21-1 eprom programming modes note : 1. 0 = valid low for that pin, 1= valid high for that pin. 2. vpp = 12.75v 0.25v 3. vdd = 5v 10% during programming and verification. 4. p3.5/prog receives 10 programming pulses while vpp is held at 12.75v. each programming pulse is low for 100 ( 10 ) and high for a minimum of 10 ?program memory lock bits the two-level program lock system consists of 2 lock bits and a 64-bytes encryption array which are used to protect the program mem- ory against software piracy. table 21-2lock bit protection modes read signature verify code data program code data program encryption table program lock bit 1 program lock bit 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 vpp vpp vpp vpp 0 0 1 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 0 1 1 0 1 0 mode reset p3.3 p3.5/ prog int0/ vpp p2.7 p2.6 p3.7 p3.6 p3.2 1 1 1 1 1 1 u : unprogrammed, p : programmed lb2 protection type u no program lock features u further programming of the eprom is disabled lb1 u p p p same as mode 2, also verify is disabled mode 1 2 3
hms9xc7132 / hms9xc7134 74 may.2001 ver1.1 ?encryption array within the eprom array are 64bytes of encryption array that are initially unprogrammed (all 1s). every time that a byte ad- dressed during a verify, address line are used to select a byte of the encryption array. this byte is then exclusive nor-ed (xnor) with the code byte, creating an encrypted verify byte. the algorithm, with the array in the unprogrammed state (all 1s), will return the code in its original, unmodified form. it is recom- mended that whenever the encryption array is used, at least one of the lock bits be programmed as well. ?reading the signature bytes the hms97c7132 signature bytes in location 30h and 20h. to read these bytes follow the procedure for eprom verify, except that p3.6 and p3.7 need to be pulled to a logic low. table 21-3 the value ?quick-pulse programming the setup for micro-controller quick-pulse programming is shown in figure 21-2. note that the hms97c7132 is running with a 4 to 6mhz oscillator. the reason the oscillator needs to be running is that the device is executing internal address and pro- gram data transfers. the address of the eprom location to be programmed is applied to port 1, 2 and vsyncin, as shown in figure 21-1. the code byte to be programmed into that location is applied to port 0. re- set, psen and pins of port2 and 3 in table 21.1 are held at the program code data levels indicated in table 21.1. the p3.5/ prog is pulsed low 10 times as shown figure 21-2. to program the encryption table, repeat the 10 pulses program- ming sequence for address 0 through 3f h, using the program encryption table levels. do not forget that after the encryption table is programmed, verification cycle will produce only en- crypted data. to program the security bits, repeat the 10 pulses programming sequence using the program security bit levels. after one se- curity bit is programmed, further programming of the code mem- ory and encryption table is disabled. however, the other security bit can still be programmed. note that int0/vpp pin must not be allowed to go above the maximum specified vpp level for any amount of time. even a narrow glitch above that voltage can cause permanent damage to the device. the vpp source should be well regulated and free glitches and overshoot. remarks device device id manufacturer id location 20h 30h hms97c7132 contents 68h adh
hms9xc7132 / hms9xc7134 may.2001 ver1.1 75 figure 21-1 programming configuration figure 21-2 prog waveform reset vdd1 vss1 xtal2 xtal1 p0 int0/vpp hsync in vsync in p2.0 -p2.5 p2.6 p2.7 p3.2/ea p3.3/psen p3.5/prog p3.6 p3.7 vdd2 vss2 p1 pgm data 12.75 v a7 - a0 a14 a13 - a8 0 1 1 0 pulse 1 1 0 p3.5/prog 10 pulses enlarged view 100 s ( 10 100s ( 10 min 10s
hms9xc7132 / hms9xc7134 76 may.2001 ver1.1 ?program verification if lock bit 2 has not been programmed, the on-chip program memory can be read out for program verification. the address of the program memory location to be read is applied to port 1, 2 and vsyncin as shown in figure 21-4. the other pins are held at the verify code data levels indicated in table 21.1. the con- tents of the address location will be emitted on port 0 for this op- eration. if the encryption table has been programmed, the data presented at port 0 will be the exclusive nor of the program byte with one of the encryption bytes. the user will have to know the encryption table contents in order to correctly decode the verifi- cation data. the encryption table itself cannot be read out. figure 21-3 verification configuration reset vdd1 vss1 xtal2 xtal1 p0 int0/vpp pgm data 5 v a7 - a0 a14 a13 - a8 0 0 1 0 1 1 1 hsync in vsync in p2.0 -p2.5 p2.6 p2.7 p3.2/ea p3.3/psen p3.5/prog p3.6 p3.7 vdd2 vss2 p1 10k w 0
hms9xc7132 / hms9xc7134 may.2001 ver1.1 77 eprom programming and verification characteristics ta = 21
to 27
, vcc = 5v + 10%, vss = 0v figure 21-4 eprom programming and verification programming supply voltage programming supply current oscillator frequency address setup to prog low address hold after prog data setup to prog data hold after prog p2.7 (enable) high to vpp vpp setup to prog vpp hold after prog prog width address to data valid enable low to data valid data float after enable prog high to prog low vpp ipp 1/ t clcl t avgl t ghax t dvgl t ghdx t ehsh t shgl t ghsl t glgl t avqv t elqv t ehqz t ghgl 12.5 - 4 48 t clcl 48 t clcl 48 t clcl 48 t clcl 48 t clcl 10 10 90 - - 0 10 13.0 50 6 - - - - - - - 110 48 t clcl 48 t clcl 48 t clcl - v ma mhz - - - - - s s s - - - s parameter symbol limit values min max unit p1.0 - p1.7 p2.0 - p2.5 vsync in port0 p3.5/prog int0/vpp p2.7(enable) // // // // // // // programming verification address address data in data out t dvgl t avgl 10 pulses t ghdx t ghax t avqv t elqv t ehqz t ehsh t ghgl t glgl t shgl t ghsl
hms9xc7132 / hms9xc7134 78 may.2001 ver1.1 21.2 64mqfp pinning and package dimensions 1 2 3 4 5 7 8 9 10 11 6 44 42 41 40 39 37 36 35 34 33 38 64 63 62 61 60 58 57 56 55 54 59 20 21 23 24 25 26 27 22 hm s97c7132 yyww 12 13 14 15 16 29 30 31 32 28 48 47 46 45 53 52 43 n.c n.c vdd1 vss1 xtal2 xtal1 bp2.7 bp2.6 sda2**/p1.7 scl2**/p1.6 bp2.5 bp2.4 p0.7 p0.6 p0.5 p0.4 in t0/v pp p0.3 p0.2 p0.1 p0.0 bp2.3 bp2.2 ach3/p1.5 ach2/p1.4 ach1/p1.3 ach0/p1.2 sda1 **/p1.1 scl1 **/p1.0 n.c pwm4*/p2.6 pwm5*/p2.7 hsync out /p 3.2 vsync out /p 3.3 pwm6*/p3.4/int1 bp2.0 bp2.1 clamp/pwm7/p3.5/prog patout/p3.6 sog in /p 3.7 rstout vdd2 vss2 n.c n.c reset p3.0 p3.1 dpw m0*/p2.0 dpw m1*/p2.1 pwm0*/p2.2 ean ale psenn vsync in hsync in pwm1*/p2.3 pwm2*/p2.4 17 18 19 n.c n.c n.c 51 50 49 pwm3*/p2.5 n.c n.c 3.18 max note 1. dimensions do not include mold protrusion and dambar protrusion. allowable mold protrusion is 0.254mm. allowable dambar protrusion shall be 0.08mm total at maximum material condition. 2. formed lead shall be planar with respect another within 0.10mm 3. controlling dimension : millimeter. this outline confirms to jedec publication 95 resistration mo-112.
hms9xc7132 / hms9xc7134 may.2001 ver1.1 79 21.3 64mqfp pin description pin name (alternate) pin no. in/out (alter- nate) function basic alternate n.c 1 - no connection n.c 2 - no connection v dd1 3 - power supply1(+5v) v ss1 4 - ground1 xtal2 5 o oscillator output pin for system clock xtal1 6 i oscillator input pin for system clock bp2.7 7 i/o external access / emulation port2.7 bp2.6 8 i/o external access / emulation port2.6 sda2 /p1.7 9 i/o general i/o port p1.7 i 2 c serial data i/o port scl2 /p1.6 10 i/o general i/o port p1.6 i 2 c serial clock i/o port bp2.5 11 i/o external access / emulation port2.5 bp2.4 12 i/o external access / emulation port2.4 p0.7 13 i/o general i/o port p0.7; adapted for led driver p0.6 14 i/o general i/o port p0.6; adapted for led driver p0.5 15 i/o general i/o port p0.5 p0.4 16 i/o general i/o port p0.4 n.c 17 - no connection n.c 18 - no connection n.c 19 - no connection int0 /v pp 20 i external interrupt input0; programming supply voltage (during otp programming) p0.3 21 i/o general i/o port p0.3 p0.2 22 i/o general i/o port p0.2 p0.1 23 i/o general i/o port p0.1 p0.0 24 i/o general i/o port p0.0 bp2.3 25 i/o external access / emulation port2.3 bp2.2 26 i/o external access / emulation port2.2 ach3 /p1.5 27 i/o general i/o port p1.5 adc channel3 input ach2 /p1.4 28 i/o general i/o port p1.4 adc channel2 input ach0 /p1.3 29 i/o general i/o port p1.3 adc channel1 input ach0 /p1.2 30 i/o general i/o port p1.2 adc channel0 input sda1 /p1.1 31 i/o general i/o port p1.1 i 2 c serial data i/o port for ddc interface scl1 /p1.0 32 i/o general i/o port p1.0 i 2 c serial clock i/o port for ddc interface n.c 33 - no connection n.c 34 - no connection v ss2 35 - ground2 v dd2 36 - power supply2(+5v) rstout 37 o reset or internal reset out / eh-ic reset signal; active high sogin /p3.7 38 i/o general i/o port p3.7 sync on green input table 21-4 port function description(64mqfp)
hms9xc7132 / hms9xc7134 80 may.2001 ver1.1 patout /p3.6 39 i/o general i/o port p3.6 pattern out clamp /pwm7 / p3.5 /prog 40 i/o general output only port p3.5 program pulse input(during otp programming) clamp out ; 8-bit pulse width modulation output7 bp2.1 41 i/o external access / emulation port2.1 bp2.0 42 i/o external access / emulation port2.0 pwm6 /p3.4 int1 43 i/o general i/o port p3.4 8-bit pulse width modulation output6; external interrupt input1 vsyncout /p3.3 44 i/o general i/o port p3.3 vertical sync output hsyncout /p3.2 45 i/o general i/o port p3.2 horizontal sync output pwm5 /p2.7 46 i/o general i/o port p2.7 8-bit pulse width modulation output5 pwm4 /p2.6 47 i/o general i/o port p2.6 8-bit pulse width modulation output4 n.c 48 - no connection n.c 49 - no connection n.c 50 - no connection pwm3 /p2.5 51 i/o general i/o port p2.5 8-bit pulse width modulation output3 pwm2 /p2.4 52 i/o general i/o port p2.4 8-bit pulse width modulation output2 pwm1 /p2.3 53 i/o general i/o port p2.3 8-bit pulse width modulation output1 hsyncin 54 i horizontal sync input vsyncin 55 i vertical sync input psenn 56 i/o program store enable not / emulation psen ale 57 i/o address latch enable / emulation ale ean 58 i/o external access not / emulation ea pwm0 /p2.2 59 i/o general i/o port p2.2 8-bit pulse width modulation output0 dpwm0 /p2.1 60 i/o general i/o port p2.1 8-bit dynamic pulse width modulation output0 dpwm0 /p2.0 61 i/o general i/o port p2.0 8-bit dynamic pulse width modulation output1 p3.1 62 i/o general i/o port p3.1 p3.0 63 i/o general i/o port p3.0 reset 64 i reset input pin name (alternate) pin no. in/out (alter- nate) function basic alternate table 21-4 port function description(64mqfp)
hms9xc7132 / hms9xc7134 may.2001 ver1.1 81 21.4 development tools the hms9xc7132 is supported by a full-featured macro assembler / linker , an in-circuit emulator metaice tm . figure 21-5 developement system hardware blockdiagram product developer an agency in korea in circuit emulators metaice zeusemtek(www.emtek.co.kr) compiler keil c51 compiler, a51/a251 assembler/linker hankook mds(www.hkmds.com) debugger xhp3051.exe (source-level debugging) pc monitor board metalink icemaster-sf converter pod power rs-232 emulator
hms9xc7132 / hms9xc7134 82 may.2001 ver1.1 22. instruction set the hms9xc7132 uses a powerful instruction set which permits the expansion of on-chip cpu peripherals and optimizes byte ef- ficiency and execution speed. assigned opcodes add new high- power operation and permit new addressing modes. the instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. when using a 12mhz oscillator, 64 in- structions execute in 1us and 45 instructions execute in 2us. mul- tiply and divide instructions execute in 4 us. for the description of the date addressing modes and hexadeci- mal opcode cross-reference see boolean variable manipula- tion,program brranching. ?arithmatic operations mnemonic description bytes cycles hex code add a, rn add register to a 1 1 2x add a, direct add direct byte to a 2 1 25 add a, @ri add indirect ram to a 1 1 26,27 add a, #data add immediate data to a 2 1 24 addc a, rn add register to a with carry flag 1 1 3x addc a, direct add direct byte to a with carry flag 2 1 35 addc a, @ri add indirect ram to a with carry flag 1 1 36,37 addc a, #data add immediate data to a with carry flag 2 1 34 subb a, rn subtract register from a with borrow 1 1 9x subb a, direct subtract direct byte from a with borrow 2 1 95 subb a, @ri subtract indirect ram from a with borrow 1 1 96,97 subb a, #data subtract immediate data from a with borrow 1 1 94 inc a increment a 1 1 04 inc rn increment register 1 1 0x inc direct increment direct byte inc @ri increment indirect ram 1 1 06,07 dec a decrement a 1 1 14 dec rn decrement rn 1 1 1x dec direct decrement direct byte 2 1 15 dec @ri decrement indirect ram 1 1 16,17 inc dtpr increment data pointer 1 2 a3 mul ab multiply a and b 1 4 a4 div ab divide a by b 1 4 84 da a decimal adjust a 1 1 d4
hms9xc7132 / hms9xc7134 may.2001 ver1.1 83 ?logical operations ?data transfer mnemonic description bytes cycles hex code anl a, rn and register to a 1 1 5x anl a, direct and direct byte to a 2 1 55 anl a, @ri and indirect ram to a 1 1 56,57 anl a, #data and immediate data to a 2 1 54 anl direct, a and a to direct byte 2 1 52 anl direct, #data and immediate data to direct byte 3 2 53 orl a, rn or register to a 1 1 4x orl a, direct or direct byte to a 2 1 45 orl a, @ri or indirect ram to a 1 1 46,47 orl a, #data or immediate data to a 2 1 44 orl direct, a or a to direct byte 2 1 42 orl direct, #data or immediate data to direct byte 3 2 43 xrl a, rn exclusive-or register to a 1 1 6x xrl a, direct exclusive-or direct byte to a 2 1 65 xrl a, @ri exclusive-or indirect ram to a 2 1 66,67 xrl a, #data exclusive-or immediate data to a 2 1 64 xrl direct, a exclusive-or a to direct byte 2 1 62 xrl direct, #data exclusive-or immediate data to direct byte 3 2 63 clr a clear a 1 1 e4 cpl a complement a 1 1 f4 rl a rotate a left 1 1 23 rlc a rotate a left through the carry flag 1 1 33 rr a rotate a right 1 1 03 rrc a rotate a right through the carry flag 1 1 13 swap a swap nibbles within a 1 1 c4 mnemonic description bytes cycles hex code mov a, rn move register to a 1 1 ex mov a, direct move direct byte to a 2 1 e5 mov a, @ri move indirect ram to a 1 1 e6,e7 mov a, #data move immediate data to a 2 1 74 mov rn, a move a to register 1 1 fx mov rn, direct move direct byte to register 2 2 ax mov rn, #data move immediate data to register 2 1 7x mov direct, a move a to direct byte 2 1 f5 mov direct, rn move register to direct byte 2 2 8x mov direct, direct move direct byte to direct byte 3 2 85
hms9xc7132 / hms9xc7134 84 may.2001 ver1.1 ?boolean variable manipulation note: * this command is not available under otp emulation mode mnemonic description bytes cycles hex code mov direct, @ri move indirect ram to direct byte 2 2 86,87 mov direct, #data move immediate data to direct byte 3 2 75 mov @ri, a move a to indirect ram 1 1 f6,f7 mov @ri, direct move direct byte to indirect ram 2 2 a6,a7 mov @ri, #data move immediate data to indirect ram 2 1 76,77 mov dptr, #data16 load data pointer with a 16-bit constant 3 2 90 movc a, @a+dptr move code byte relative to dptr to a 1 2 93 movc a, @a+c move code byte relative to pc to a 1 2 83 movx a, @ri move external ram (8-bit address) to a 1 2 e2,e3 movx a, @dptr move external ram (16-bit address) to a 1 2 e0 movx @ri, a move a to external ram (8-bit address) 1 2 f2,f3 movx @dptr, a move a to external ram (16-bit address) 1 2 f0 push direct push direct byte onto stack 2 2 c0 pop direct pop direct byte from stack 2 2 d0 xch a, rn exchange register with a 1 1 cx xch a, direct exchange direct byte with a 2 4 c5 xch a, @ri exchange indirect ram with a 1 1 c6,c7 xchd a, @ri exchange low-order digit indirect ram with a 1 1 d6,d7 mnemonic description bytes cycles hex code clr c clear carry flag 1 1 c3 clr bit clear direct bit 2 1 c2 setb c set carry flag 1 1 d3 setb bit set direct bit 2 1 d2 cpl c complement carry flag 1 1 b3 cpl bit complement direct bit 2 1 b2 anl c, bit and direct bit to carry flag 2 1 82 anl c, /bit and complement of direct bit to carry flag 2 2 b0 or c, bit or direct bit to carry flag 2 2 72 or c, /bit or complement of direct bit to carry flag 2 2 a0 mov c, bit move direct bit to carry flag 2 1 a2 *mov bit, c move carry flag to direct bit 2 2 92 jc rel jump if carry flag is set 2 2 40 jnc rel jump if carry flag is not set 2 2 50 jb bit, rel jump if direct bit is set 3 2 20 jnb bit, rel jump if direct bit is not set 3 2 30 jbc bit, rel jump if direct bit is set and clear bit 3 2 10
hms9xc7132 / hms9xc7134 may.2001 ver1.1 85 ?program branching ?data addressing modes mnemonic description bytes cycles hex code acall addr11 absolute subroutine call 2 2 y1 lcall addr16 long subroutine call 3 1 12 ret return from subroutine 1 2 22 reti return from interrupt 2 2 32 ajmp addr16 absolute jump 2 2 z1 ljmp addr16 long jump 3 2 02 sjmp addr16 short jump(relative address) 2 2 80 jmp @a+dptr jump indirect relative to the dptr 1 2 73 jz rel jump if a is zero 2 2 60 jnz rel jump if a is not zero 2 2 70 cjne a, direct, rel compare direct byte to a and jump if not equal 3 2 b5 cjne a, #data, rel compare immediate data to a and jump if not equal 3 2 b4 cjne rn, #data, rel compare immediate data to register and jump if not equal 32bx cjne a, @ri, rel compare immediate data to indirect ram and jump if not equal 32b6,b7 djnz rn, rel decrement register and jump if not zero 2 2 dx djnz direct, rel decrement direct byte and jump if not zero 3 2 d5 nop no operation 1 1 00 mnemonic description rn working register r0-r7 direct 128 internal ram locations and any special function register (sfr) @ri indirect internal ram location addressed by register by register r0 or r1 of the actual register bank #data 8-bit constant included in instruction #data16 16-bit constant included as bytes 2 and 3 of instruction bit direct addressed bit in internal ram or sfr addr16 16-bit destination address. used by lcall and ljmp; the branch will be anywhere within the 64 kbytes program memory address space addr11 111-bit destination address. used by acall and ajmp;the branch will be within the same 2 kbytes page of program memory as the first byte of the following instruction rel signed(two?s complement) 8-bit offset byte. used by sjmp and all conditional jumps; range is - 128 to + 127 bytes relative to first byte of the following instruction
hms9xc7132 / hms9xc7134 86 may.2001 ver1.1 ?hexadecimal opcode cross-reference mnemonic description x 8, 9, a, b, c, d, e, f y 1, 3, 5, 7, 9, b, d, f z 0, 2, 4, 6, 8, a, c, e

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